2014 27th IEEE International System-on-Chip Conference (SOCC)
Latest Publications

TOTAL DOCUMENTS

102

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781479933785

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

2014 27th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2014.6948972 ◽

2014 ◽

Cited By ~ 1

Author(s):

Chao-Kuei Chung ◽

Chien-Yu Lu ◽

Zhi-Hao Chang ◽

Shyh-Jye Jou ◽

Ching-Te Chuang ◽

...

Keyword(s):

Threshold Power ◽

Power Gating ◽

Charge Sharing ◽

Source Line ◽

Negative Source

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Design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique

2014 27th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2014.6948904 ◽

2014 ◽

Cited By ~ 1

Author(s):

Jongyoon Hwang ◽

Dongjoo Kim ◽

Mun-Kyo Lee ◽

Sun-Phil Nah ◽

Minkyu Song

Keyword(s):

Error Reduction ◽

Reduction Technique

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Flexible reconfigurable architecture for DSP applications

2014 27th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2014.6948927 ◽

2014 ◽

Cited By ~ 3

Author(s):

Abdulfattah M. Obeid ◽

Syed Manzoor Qasim ◽

Mohammed S. BenSaleh ◽

Zied Marrakchi ◽

Habib Mehrez ◽

...

Keyword(s):

Reconfigurable Architecture ◽

Dsp Applications

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Design of a low power multistandard transceiver chain based on current-reuse VCO

2014 27th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2014.6948961 ◽

2014 ◽

Author(s):

Ye Zhang ◽

Jan Henning Mueller ◽

Muh-Dey Wei ◽

Ralf Wunderlich ◽

Stefan Heinen

Keyword(s):

Low Power ◽

Current Reuse

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Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs

2014 27th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2014.6948947 ◽

2014 ◽

Cited By ~ 6

Author(s):

Hiroyuki Yamauchi ◽

Worawit Somha

Keyword(s):

Inverse Problem ◽

Screening Test

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T2B: Carbon nanotubes and opportunities for wireless on-chip interconnect

2014 27th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2014.6948884 ◽

2014 ◽

Author(s):

Alireza Nojeh ◽

Partha P. Pande ◽

Andre Ivanov

Keyword(s):

Carbon Nanotubes ◽

On Chip

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Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation

2014 27th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2014.6948897 ◽

2014 ◽

Cited By ~ 2

Author(s):

Shinichi Nishizawa ◽

Tohru Ishihara ◽

Hidetoshi Onodera

Keyword(s):

Design Methodology ◽

Low Voltage ◽

Process Variation

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Electromyograph data acquisition and application using Cypress Programmable System on Chip

2014 27th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2014.6948910 ◽

2014 ◽

Cited By ~ 2

Author(s):

Shreeyash Salunke ◽

Shreyas Darne ◽

Keval Shah ◽

Rishikesh Dhamapurkar

Keyword(s):

Data Acquisition ◽

System On Chip ◽

On Chip

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T1B: Wireless NoC as interconnection backbone for multicore chips: Promises and challenges

2014 27th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2014.6948883 ◽

2014 ◽

Cited By ~ 1

Author(s):

Partha P. Pande ◽

Alireza Nojeh ◽

Andre Ivanov

Keyword(s):

Multicore Chips

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[Front cover]

2014 27th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2014.6948871 ◽

2014 ◽

Keyword(s):

Front Cover

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2014 27th IEEE International System-on-Chip Conference (SOCC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

Design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique

Flexible reconfigurable architecture for DSP applications

Design of a low power multistandard transceiver chain based on current-reuse VCO

Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs

T2B: Carbon nanotubes and opportunities for wireless on-chip interconnect

Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation

Electromyograph data acquisition and application using Cypress Programmable System on Chip

T1B: Wireless NoC as interconnection backbone for multicore chips: Promises and challenges

[Front cover]

2014 27th IEEE International System-on-Chip Conference (SOCC)
Latest Publications