Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation

2014 ◽  
Author(s):  
Shinichi Nishizawa ◽  
Tohru Ishihara ◽  
Hidetoshi Onodera
Keyword(s):  
Design Methodology ◽  
Low Voltage ◽  
Process Variation

DESIGN OF MODIFIED FOUR-PHASE CMOS CHARGE PUMPS FOR LOW-VOLTAGE FLASH MEMORIES

2002 ◽  
Vol 11 (04) ◽  
pp. 393-403 ◽  
Author(s):  
HONGCHIN LIN ◽  
NAI-HSIEN CHEN ◽  
JAINHAO LU
Keyword(s):  
Power Efficiency ◽  
Design Methodology ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Flash Memories ◽  
Clock Generation ◽  
Charge Pumps ◽  
Main Charge

A new four-phase clock scheme for the four-phase charge pumping circuits using standard 0.5 μm CMOS technology at low supply voltages to generated high boosted voltages is proposed. Boosted clocks without high drivability are applied on the capacitors coupled to the gates of the main charge transfer transistors to compensate body effects. Thus, the high-voltage clock generation circuit can be easily achieved for clock frequency of 10 MHz. Due to the nearly ideal pumping gain per stage, the design methodology to optimize power efficiency is also presented. With the new clock scheme, it can efficiently pump to 9 V at supply voltage of 1 V using 10 stages by simulations, while pump to 4.7 V at supply voltage of 1.5 V using four stages by measurements.

Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier

2015 ◽  
Vol 16 (8) ◽  
pp. 700-706 ◽  
Author(s):  
Shou-biao Tan ◽  
Wen-juan Lu ◽  
Chun-yu Peng ◽  
Zheng-ping Li ◽  
You-wu Tao ◽  
...  
Keyword(s):  
Low Voltage ◽  
Process Variation ◽  
Sense Amplifier ◽  
Multi Stage

Design Methodology of High Frequency M-ary ASK, FSK and QAM

2015 ◽  
Vol 24 (10) ◽  
pp. 1550152 ◽  
Author(s):  
Mousumi Bhanja ◽  
Surya Prakash Tamang ◽  
Ritika Das ◽  
Baidyanath Ray
Keyword(s):  
High Frequency ◽  
High Speed ◽  
Design Methodology ◽  
Low Voltage ◽  
Signal Distortion ◽  
Eye Diagram ◽  
High Data ◽  
Transconductance Amplifier ◽  
Level Converter ◽  
Diagram Analysis

This paper proposes a high data rate, low-power, low-voltage design of OTA-based M-ary ASK, FSK and QAM modulator and demodulator circuits. Conventional D/A converter of M-ary circuit has been replaced with the operational transconductance amplifier-based n-bits to 2n level converter which operates with input frequencies up to 2.1 GHz. OTA-based oscillator and PLL is being designed for high speed M-ary FSK. Eye diagram analysis has been carried out, conforming a very low signal distortion. Theoretical analysis of bit error rate has been done. The circuit analysis and simulation results confirm the reliability and accuracy of the design. Effective layouts and die photographs of the proposed designs are also presented.

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