Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic
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Published By IEEE Comput. Soc

0769514626

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Efficient bridging fault simulation of sequential circuits based on multi-valued logics

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic ◽

10.1109/ismvl.2002.1011092 ◽

2003 ◽

Cited By ~ 6

Author(s):

I. Polian ◽

P. Engelke ◽

B. Becker

Keyword(s):

Fault Simulation ◽

Sequential Circuits ◽

Bridging Fault

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Voltage comparator circuits for multiple-valued CMOS logic

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic ◽

10.1109/ismvl.2002.1011072 ◽

2003 ◽

Cited By ~ 4

Author(s):

Y.B. Guo ◽

K.W. Current

Keyword(s):

Voltage Comparator

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On the construction of multiple-valued decision diagrams

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic ◽

10.1109/ismvl.2002.1011095 ◽

2003 ◽

Cited By ~ 32

Author(s):

D.M. Miller ◽

R. Drechsler

Keyword(s):

Decision Diagrams

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Logic for static hazard detection of multiple-valued logic circuits with TSUM, MIN, and Literals

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic ◽

10.1109/ismvl.2002.1011069 ◽

2003 ◽

Cited By ~ 2

Author(s):

N. Tkagi ◽

K. Nakashima

Keyword(s):

Logic Circuits ◽

Multiple Valued Logic ◽

Hazard Detection

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Multiple-valued logic-in-memory VLSI based on ferroelectric capacitor storage and charge addition

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic ◽

10.1109/ismvl.2002.1011085 ◽

2003 ◽

Author(s):

H. Kimura ◽

T. Hanyu ◽

M. Kameyama

Keyword(s):

Ferroelectric Capacitor ◽

Multiple Valued Logic ◽

Capacitor Storage

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Sierpinski gaskets for logic functions representation

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic ◽

10.1109/ismvl.2002.1011068 ◽

2003 ◽

Cited By ~ 5

Author(s):

D.V. Popel ◽

A. Dani

Keyword(s):

Sierpinski Gaskets ◽

Logic Functions

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Some remarks on linear transform of variables in representation of adders by word-level expressions and spectral transform decision diagrams

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic ◽

10.1109/ismvl.2002.1011078 ◽

2003 ◽

Cited By ~ 3

Author(s):

R.S. Stankovic ◽

J.T. Astola

Keyword(s):

Decision Diagrams ◽

Word Level ◽

Spectral Transform ◽

Linear Transform

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Improving the characterization of p-valued threshold functions

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic ◽

10.1109/ismvl.2002.1011066 ◽

2003 ◽

Cited By ~ 1

Author(s):

C. Moraga

Keyword(s):

Threshold Functions

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Partial hyperclones on a finite set

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic ◽

10.1109/ismvl.2002.1011064 ◽

2003 ◽

Cited By ~ 12

Author(s):

B.A. Romov

Keyword(s):

Finite Set

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Evaluation of static variable ordering heuristics for MDD construction [multi-valued decision diagrams]

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic ◽

10.1109/ismvl.2002.1011096 ◽

2003 ◽

Cited By ~ 5

Author(s):

R. Drechsler

Keyword(s):

Decision Diagrams ◽

Variable Ordering ◽

Variable Ordering Heuristics

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Proceedings 32nd IEEE International Symposium on Multiple- Valued LogicLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Efficient bridging fault simulation of sequential circuits based on multi-valued logics

Voltage comparator circuits for multiple-valued CMOS logic

On the construction of multiple-valued decision diagrams

Logic for static hazard detection of multiple-valued logic circuits with TSUM, MIN, and Literals

Multiple-valued logic-in-memory VLSI based on ferroelectric capacitor storage and charge addition

Sierpinski gaskets for logic functions representation

Some remarks on linear transform of variables in representation of adders by word-level expressions and spectral transform decision diagrams

Improving the characterization of p-valued threshold functions

Partial hyperclones on a finite set

Evaluation of static variable ordering heuristics for MDD construction [multi-valued decision diagrams]

Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic
Latest Publications