The fourth fundamental circuit element: principle and applications

The relationships between four basic circuit variables - voltage (v), current (i), charge (q), and magnetic flux (ϕ) - have defined three fundamental circuit elements: resistor, capacitor, and inductor. From a symmetry view, there is a fourth fundamental circuit element defined from the relationship between charge and magnetic flux. Historically, a device called memristor was considered to be the fourth element, but it has caused intense controversy because the memristor is conceived based on a nonlinear i-v relationship rather than a direct q-ϕ relationship. Alternatively, a direct correlation between trapped charge (q) and magnetic flux (ϕ) can be built up by employing the magnetoelectric (ME) effects, i.e., magnetic field control of electric polarization and electric field control of magnetization. In this review, we summarize recent progress on the principle and applications of the fourth circuit element based on the ME effects. Both the fourth linear element and nonlinear memelement, termed transtor and memtranstor, respectively, have been proposed and experimentally demonstrated. A complete relational diagram of fundamental circuit elements has been constructed. The transtor with a linear ME effect can be used in a variety of applications such as the energy harvester, tunable inductor, magnetic sensor, gyrator, and transformer etc. The memtranstor showing a pinched hysteresis loop has a great potential in developing low-power nonvolatile electronic devices. The principle is to utilize the states of the ME coefficient αE=dE/dH, instead of resistance, magnetization or electric polarization to store information. Both nonvolatile memories and logic functions can be implemented using the memtranstors, which provides a candidate route toward the logic-in-memory computing system. In addition, artificial synaptic devices that are able to mimic synaptic behaviors have also been realized using the memtranstor. The fourth circuit element and memelement based on the ME effects provide extra degrees of freedom to broaden circuit functionalities and develop advanced electronic devices.

An application-specific image processing array based on WSe2 transistors with electrically switchable logic functions

With the rapid development of artificial intelligence, parallel image processing is becoming an increasingly important ability of computing hardware. To meet the requirements of various image processing tasks, the basic pixel processing unit contains multiple functional logic gates and a multiplexer, which leads to notable circuit redundancy. The pixel processing unit retains a large optimizing space to solve the area redundancy issues in parallel computing. Here, we demonstrate a pixel processing unit based on a single WSe2 transistor that has multiple logic functions (AND and XNOR) that are electrically switchable. We further integrate these pixel processing units into a low transistor-consumption image processing array, where both image intersection and image comparison tasks can be performed. Owing to the same image processing power, the consumption of transistors in our image processing unit is less than 16% of traditional circuits.

Mapping Arbitrary Logic Functions onto Carry Chains in FPGAs

Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non-arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike other approaches, the proposed technique can be applied to any logic function. The presented technique includes: (1) an architecture that is composed of blocks that implement AND and OR functions (called CANDs and CORs, respectively) by means of Look-Up-Tables (LUTs) and carry-chain resources; and (2) a mapping algorithm to reduce both the delay of the critical path and the number of used FPGA resources. The algorithm uses a heuristic to interconnect CORs and CANDs in order to reduce the delay. The problem of mapping the maxterms (or minterms) of a function to LUTs has been modelled as a Set Bin Packing (SBP) problem. Since SBP is NP-Hard, a greedy algorithm has been proposed, which is based on the First Fit Decreasing (FFD) heuristic. The results obtained have been compared with the conventional technique using both speed and area optimization. For this purpose, a large synthetic set of test cases has been generated. The proposed technique improves both the speed and area results for the vast majority of functions whose conventional implementation requires more than four logic levels. It is important to highlight that the improvement of one parameter (speed or area) is not achieved at the expense of the other.

Light/electric modulated approach for logic functions and artificial synapse behaviors by flexible IGZO TFTs with low power consumption

In recent years, low power electronic devices have attracted more and more interests. Here, flexible thin-film transistors(TFTs) with In-Ga-Zn-O (IGZO) as semiconductor channel material were fabricated on polyethylene terephthalate (PET) substrates. The device exhibits good electrical properties at low operating voltage, including high on/off ratio of ~ 7.8 × 106 and high electron mobility of ~ 23.1 cm2V-1s-1. The device also has excellent response characteristics to visible light. With the increase of visible light intensity, the threshold voltage of IGZO TFTs decreases continuously, but the electron mobility increases gradually. Based on the unique response ability of the device to light, we proposed and demonstrated that a single thin-film transistor can realize different logic operations under the light/electricity mixed modulation, including “AND” and “OR”. In addition, we also simulated some basic artificial synaptic behaviors, including excitatory postsynaptic current and paired-pulse facilitation. Thus, IGZO TFTs operating at low voltages not only have the potential to construct multifunctional optoelectronic devices, but also provide a new idea for simplifying the design of programmable logic circuits.

Method for analytical description and modeling of the working space of a manipulation robot

This paper reports a method, built in the form of a logic function, for describing the working spaces of manipulation robots analytically. A working space is defined as a work area or reachable area by a manipulation robot. An example of describing the working space of a manipulation robot with seven rotational degrees of mobility has been considered. Technological processes in robotic industries can be associated with the positioning of the grip, at the required points, in the predefined coordinates, or with the execution of the movement of a working body along the predefined trajectories, which can also be determined using the required points in the predefined coordinates. A necessary condition for a manipulation robot to execute a specified process is that all the required positioning points should be within a working space. To solve this task, a method is proposed that involves the analysis of the kinematic scheme of a manipulation robot in order to acquire a graphic image of the working space to identify boundary surfaces, as well as identify additional surfaces. The working space is limited by a set of boundary surfaces where additional surfaces are needed to highlight parts of the working space. Specifying each surface as a logic function, the working space is described piece by piece. Next, the resulting parts are combined with a logical expression, which is a disjunctive normal form of logic functions, which is an analytical description of the working space. The correspondence of the obtained analytical description to the original graphic image of working space is verified by simulating the disjunctive normal form of logic functions using MATLAB (USA).

MATHEMATICAL MODELS OF HOMOGENEOUS ELEMENTS MAX, MIN BASED ON TWO-DIGIT LOGIC FUNCTIONS

Examples of using two-digit logical functions to describe basic operations of multi-valued logic are discussed.

Design of ternary subtractor using multiplexers

Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.

Reconfigurable nonvolatile boolean logic with one-transistor-two-memristor for in-memory computing

In-memory computing is highly expected to break the von Neumann bottleneck and memory wall. Memristor with inherent nonvolatile property is considered to be a strong candidate to execute this new computing paradigm. In this work, we have presented a reconfigurable nonvolatile logic method based on one-transistor-two-memristor (1T2M) device structure, inhibiting the sneak path in the large-scale crossbar array. By merely adjusting the applied voltage signals, all 16 binary Boolean logic functions can be achieved in a single cell. More complex computing tasks including one-bit parallel full adder and Set-Reset latch have also been realized with optimization, showing simple operation process, high flexibility, and low computational complexity. The circuit verification based on cadence PSpice simulation is also provided, proving the feasibility of the proposed design. The work in this paper is intended to make progress in constructing architectures for in-memory computing paradigm.

In-Memory Computing on Resistive RAM Systems Using Majority Operation

Memristors can be used to build nonvolatile memory systems with in-memory computing (IMC) capabilities. A number of prior works demonstrate the design of an IMC-capable memory macro using a memristor crossbar. However, read disturbance limits the use of such memory systems built using a 0-transistor, 1-RRAM (0T1R) structure that suffers from the sneak path problem. In this paper, we introduce a scheme for both memory and logic operations using the 1-transistor, 1-RRAM (1T1R) memristor crossbar, which effectively mitigates the read disturbance problem. The memory array is designed using nMOS transistors and the VTEAM memristor model. The peripheral circuitry like decoders, voltage multiplexers, and sense amplifiers is designed using a 45[Formula: see text]nm CMOS technology node. We introduce a mapping technique to realize arbitrary logic functions using Majority (MAJ) gate operations in the 1T1R crossbar. Through extensive experimentation on benchmark functions, it has been found that the proposed mapping method gives an improvement of 65% or more in terms of the number of time steps required, and 59% or more in terms of energy consumption as compared to some of the recent methods.