2018 IEEE Symposium on VLSI Circuits
Latest Publications

TOTAL DOCUMENTS

113

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781538642146

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A 10-Bit 20–40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502268 ◽

2018 ◽

Cited By ~ 2

Author(s):

Lukas Kull ◽

Danny Luu ◽

Christian Menolfi ◽

Thomas Morf ◽

Pier Andrea Francese ◽

...

Keyword(s):

First Order

A 220 M-Range Direct Time-of-Flight 688 × 384 CMOS Image Sensor with Sub-Photon Signal Extraction (SPSE) Pixels Using Vertical Avalanche Photo-Diodes and 6 KHz Light Pulse Counters

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502408 ◽

2018 ◽

Cited By ~ 1

Author(s):

Shinzo Koyama ◽

Motonori Ishii ◽

Shigeru Saito ◽

Masato Takemoto ◽

Yugo Nose ◽

...

Keyword(s):

Light Pulse ◽

Time Of Flight ◽

Cmos Image Sensor ◽

Image Sensor ◽

Signal Extraction ◽

Photon Signal

AMASS PLL: An Active-Mixer-Adopted Sub-Sampling PLL Achieving an FOM of −255.5DB and a Reference Spur of −66.6DBC

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502425 ◽

2018 ◽

Cited By ~ 3

Author(s):

Dhon-Gue Lee ◽

Patrick P. Mercier

Keyword(s):

Active Mixer ◽

Reference Spur

A Sub-Leakage PW-Power HZ-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated Supply

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502413 ◽

2018 ◽

Cited By ~ 5

Author(s):

Orazio Aiello ◽

Paolo Crovetti ◽

Massimo Alioto

Keyword(s):

Relaxation Oscillator

New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502399 ◽

2018 ◽

Cited By ~ 1

Author(s):

K. Kakushima ◽

T. Hoshii ◽

M. Watanabe ◽

N. Shizyo ◽

K. Furukawa ◽

...

Keyword(s):

Carrier Lifetime ◽

Minority Carrier ◽

Minority Carrier Lifetime ◽

Process Assessment

A 12-Bit 31.1UW 1MS/S SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4DB SFDR Using 256FF Sampling Capacitance

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502325 ◽

2018 ◽

Cited By ~ 3

Author(s):

Junhua Shen ◽

Akira Shikata ◽

Anping Liu ◽

Frederick Chalifoux

Keyword(s):

Input Signal ◽

Sar Adc ◽

On Chip ◽

Independent Calibration

A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502384 ◽

2018 ◽

Cited By ~ 1

Author(s):

Biao Wang ◽

Sai-Weng Sin ◽

U Seng-Pan ◽

Franco Malobertr ◽

R. P. Martins

A 95.3% Peak Efficiency, 135NA Quiescent Current Buck-Boost DC-DC Converter with Current-Slope-Based Mode Control

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502407 ◽

2018 ◽

Cited By ~ 1

Author(s):

Danzhu Lu ◽

Peng Liu ◽

Suyi Yao ◽

Langyuan Wang ◽

Jie He

Keyword(s):

Peak Efficiency ◽

Mode Control ◽

Quiescent Current

A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G Operation for Enhancing Power Back-off Efficiency

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502364 ◽

2018 ◽

Cited By ~ 2

Author(s):

Aoyang Zhang ◽

Mike Shuo-Wei Chen

Keyword(s):

Power Amplifier ◽

Hybrid Class

A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS

2018 IEEE Symposium on VLSI Circuits ◽

10.1109/vlsic.2018.8502380 ◽

2018 ◽

Cited By ~ 1

Author(s):

Haram Ju ◽

Moon-Chul Choi ◽

Gyu-Seob Jeong ◽

Deog-Kyoon Jeong

Keyword(s):

Active Feedback ◽

28 Nm

2018 IEEE Symposium on VLSI CircuitsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A 10-Bit 20–40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration

A 220 M-Range Direct Time-of-Flight 688 × 384 CMOS Image Sensor with Sub-Photon Signal Extraction (SPSE) Pixels Using Vertical Avalanche Photo-Diodes and 6 KHz Light Pulse Counters

AMASS PLL: An Active-Mixer-Adopted Sub-Sampling PLL Achieving an FOM of −255.5DB and a Reference Spur of −66.6DBC

A Sub-Leakage PW-Power HZ-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated Supply

New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment

A 12-Bit 31.1UW 1MS/S SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4DB SFDR Using 256FF Sampling Capacitance

A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS

A 95.3% Peak Efficiency, 135NA Quiescent Current Buck-Boost DC-DC Converter with Current-Slope-Based Mode Control

A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G Operation for Enhancing Power Back-off Efficiency

A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS

2018 IEEE Symposium on VLSI Circuits
Latest Publications