22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03
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In memory of Bob Rau

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03 ◽

10.1109/micro.2003.1253192 ◽

2005 ◽

Author(s):

M. Schlansker

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Scalable hardware memory disambiguation for high ILP processors

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03 ◽

10.1109/micro.2003.1253244 ◽

2004 ◽

Cited By ~ 51

Author(s):

S. Sethumadhavan ◽

R. Desikan ◽

D. Burger ◽

C.R. Moore ◽

S.W. Keckler

Keyword(s):

Memory Disambiguation ◽

Scalable Hardware

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LLVA: a low-level virtual instruction set architecture

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03 ◽

10.1109/micro.2003.1253196 ◽

2004 ◽

Cited By ~ 18

Author(s):

V. Adve ◽

C. Lattner ◽

M. Brukman ◽

A. Shukla ◽

B. Gaeke

Keyword(s):

Instruction Set ◽

Instruction Set Architecture ◽

Low Level ◽

Virtual Instruction

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IA-32 execution layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium/spl reg/-based systems

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03 ◽

10.1109/micro.2003.1253195 ◽

2004 ◽

Cited By ~ 59

Author(s):

L. Baraz ◽

T. Devor ◽

O. Etzion ◽

S. Goldenberg ◽

A. Skaletsky ◽

...

Keyword(s):

Two Phase ◽

Phase Dynamic

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Processor acceleration through automated instruction set customization

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03 ◽

10.1109/micro.2003.1253189 ◽

2004 ◽

Cited By ~ 100

Author(s):

N. Clark ◽

Hongtao Zhong ◽

S. Mahlke

Keyword(s):

Instruction Set

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IPStash: a power-efficient memory architecture for IP-lookup

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03 ◽

10.1109/micro.2003.1253210 ◽

2004 ◽

Cited By ~ 14

Author(s):

S. Kaxiras ◽

G. Keramidas

Keyword(s):

Memory Architecture ◽

Power Efficient ◽

Ip Lookup ◽

Efficient Memory

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The reconfigurable streaming vector processor (RSVP/spl trade/)

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03 ◽

10.1109/micro.2003.1253190 ◽

2004 ◽

Cited By ~ 11

Author(s):

S. Ciricescu ◽

R. Essick ◽

B. Lucas ◽

P. May ◽

K. Moat ◽

...

Keyword(s):

Vector Processor

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Fast path-based neural branch prediction

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03 ◽

10.1109/micro.2003.1253199 ◽

2004 ◽

Cited By ~ 45

Author(s):

D.A. Jimenez

Keyword(s):

Branch Prediction

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Macro-op scheduling: relaxing scheduling loop constraints

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03 ◽

10.1109/micro.2003.1253202 ◽

2004 ◽

Cited By ~ 23

Author(s):

I. Kim ◽

M. Lipasti

Keyword(s):

Loop Constraints

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Exploiting value locality in physical register files

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03 ◽

10.1109/micro.2003.1253201 ◽

2004 ◽

Cited By ~ 31

Author(s):

S. Balakrishnan ◽

G.S. Sohi

Keyword(s):

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22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

In memory of Bob Rau

Scalable hardware memory disambiguation for high ILP processors

LLVA: a low-level virtual instruction set architecture

IA-32 execution layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium/spl reg/-based systems

Processor acceleration through automated instruction set customization

IPStash: a power-efficient memory architecture for IP-lookup

The reconfigurable streaming vector processor (RSVP/spl trade/)

Fast path-based neural branch prediction

Macro-op scheduling: relaxing scheduling loop constraints

Exploiting value locality in physical register files

22nd Digital Avionics Systems Conference Proceedings (Cat No 03CH37449) MICRO-03
Latest Publications