2013 23rd International Conference on Field programmable Logic and Applications
Latest Publications

TOTAL DOCUMENTS

152

(FIVE YEARS 0)

H-INDEX

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Published By IEEE

9781479900046

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Binarization based implementation for real-time human detection

2013 23rd International Conference on Field programmable Logic and Applications ◽

10.1109/fpl.2013.6645590 ◽

2013 ◽

Cited By ~ 8

Author(s):

Shuai Xie ◽

Yibin Li ◽

Zhiping Jia ◽

Lei Ju

Keyword(s):

Real Time ◽

Human Detection

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Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGAS

2013 23rd International Conference on Field programmable Logic and Applications ◽

10.1109/fpl.2013.6645512 ◽

2013 ◽

Cited By ~ 5

Author(s):

Brahim Al Farisi ◽

Karel Bruneel ◽

Dirk Stroobandt

Keyword(s):

Partial Reconfiguration ◽

Dynamic Partial Reconfiguration

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A hardware accelerated approach for imaging flow cytometry

2013 23rd International Conference on Field programmable Logic and Applications ◽

10.1109/fpl.2013.6645507 ◽

2013 ◽

Cited By ~ 3

Author(s):

Dajung Lee ◽

Pingfan Meng ◽

Matthew Jacobsen ◽

Henry Tse ◽

Dino Di Carlo ◽

...

Keyword(s):

Flow Cytometry ◽

Imaging Flow Cytometry

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Impact of hard macro size on FPGA clock rate and place/route time

2013 23rd International Conference on Field programmable Logic and Applications ◽

10.1109/fpl.2013.6645510 ◽

2013 ◽

Cited By ~ 10

Author(s):

Christopher Lavin ◽

Brent Nelson ◽

Brad Hutchings

Keyword(s):

Clock Rate

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Design Space Exploration based on multiobjective genetic algorithms and clustering-based high-level estimation

2013 23rd International Conference on Field programmable Logic and Applications ◽

10.1109/fpl.2013.6645608 ◽

2013 ◽

Cited By ~ 1

Author(s):

Luiz G. A. Martins ◽

Eduardo Marques

Keyword(s):

Genetic Algorithms ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Multiobjective Genetic Algorithms ◽

High Level Estimation ◽

High Level

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Simulation-based HW/SW co-debugging for field-programmable systems-on-chip

2013 23rd International Conference on Field programmable Logic and Applications ◽

10.1109/fpl.2013.6645542 ◽

2013 ◽

Cited By ~ 1

Author(s):

Ruediger Willenberg ◽

Paul Chow

Keyword(s):

Systems On Chip ◽

Simulation Based ◽

Field Programmable ◽

On Chip

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FPGA based hardware-software co-designed dynamic binary translation system

2013 23rd International Conference on Field programmable Logic and Applications ◽

10.1109/fpl.2013.6645554 ◽

2013 ◽

Cited By ~ 5

Author(s):

Yuan Yao ◽

Zhongyong Lu ◽

Qingsong Shi ◽

Wenzhi Chen

Keyword(s):

Translation System ◽

Binary Translation ◽

Dynamic Binary Translation

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A reconfigurable computing architecture using magnetic tunneling junction memories

2013 23rd International Conference on Field programmable Logic and Applications ◽

10.1109/fpl.2013.6645616 ◽

2013 ◽

Cited By ~ 2

Author(s):

Victor Silva ◽

Jorge Fernandes ◽

Mario Vestias ◽

Horacio Neto

Keyword(s):

Reconfigurable Computing ◽

Tunneling Junction ◽

Computing Architecture ◽

Magnetic Tunneling Junction ◽

Magnetic Tunneling

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Parallel and scalable custom computing for real-time fluid simulation on a cluster node with four tightly-coupled FPGAs

2013 23rd International Conference on Field programmable Logic and Applications ◽

10.1109/fpl.2013.6645625 ◽

2013 ◽

Author(s):

Kentaro Sano ◽

Ryo Ito ◽

Hayato Suzuki ◽

Yoshiaki Kono

Keyword(s):

Real Time ◽

Fluid Simulation ◽

Tightly Coupled

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Managing the FPGA memory wall: Custom computing or vector processing?

2013 23rd International Conference on Field programmable Logic and Applications ◽

10.1109/fpl.2013.6645538 ◽

2013 ◽

Cited By ~ 13

Author(s):

Matthew Naylor ◽

Paul J Fox ◽

A Theodore Markettos ◽

Simon W Moore

Keyword(s):

Memory Wall ◽

Vector Processing

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2013 23rd International Conference on Field programmable Logic and ApplicationsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Binarization based implementation for real-time human detection

Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGAS

A hardware accelerated approach for imaging flow cytometry

Impact of hard macro size on FPGA clock rate and place/route time

Design Space Exploration based on multiobjective genetic algorithms and clustering-based high-level estimation

Simulation-based HW/SW co-debugging for field-programmable systems-on-chip

FPGA based hardware-software co-designed dynamic binary translation system

A reconfigurable computing architecture using magnetic tunneling junction memories

Parallel and scalable custom computing for real-time fluid simulation on a cluster node with four tightly-coupled FPGAs

Managing the FPGA memory wall: Custom computing or vector processing?

2013 23rd International Conference on Field programmable Logic and Applications
Latest Publications