2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
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90nm Phase Change Technology with μTrench and Lance Cell Elements

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2007.378938 ◽

2007 ◽

Cited By ~ 3

Author(s):

G. Atwood ◽

R. Bez

Keyword(s):

Phase Change

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Amorphization and Templated Recrystallization (ATR) Study for Hybrid Orientation Technology (HOT) using Direct Silicon Bond (DSB) Substrates

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2007.378957 ◽

2007 ◽

Cited By ~ 2

Author(s):

Yao-Tsung Huang ◽

Angelo Pinto ◽

Chien-Ting Lin ◽

Che-Hua Hsu ◽

Manfred Ramin ◽

...

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A Study on the Erase and Retention Mechanisms for MONOS, MANOS, and BE-SONOS Non-Volatile Memory Devices

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2007.378898 ◽

2007 ◽

Cited By ~ 5

Author(s):

Sheng-Chih Lai ◽

Erh-Kun Lai ◽

Kuang-Yeu Hsieh ◽

Rich Liu ◽

Chih-Yuan Lu ◽

...

Keyword(s):

Memory Devices ◽

Retention Mechanisms ◽

Non Volatile Memory ◽

Volatile Memory

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Metrology and reliability of sub-45 nm Cu/ULK interconnects using multiline test structures

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2007.378953 ◽

2007 ◽

Author(s):

C. Guedj ◽

V. Arnal ◽

C. Jayet ◽

L. Arnaud

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Monolithic 3D Integrated Circuits

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2007.378923 ◽

2007 ◽

Cited By ~ 41

Author(s):

Simon Wong ◽

Abbas El-Gamal ◽

Peter Griffin ◽

Yoshio Nishi ◽

Fabian Pease ◽

...

Keyword(s):

Integrated Circuits ◽

3D Integrated Circuits

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Impact of advanced process modules and device architectures on the matching performance of (sub-)45nm CMOS

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2007.378968 ◽

2007 ◽

Author(s):

C. Gustin ◽

A. Mercha ◽

J. Loo ◽

B. Parvais ◽

V. Subramanian ◽

...

Keyword(s):

Matching Performance

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To Analyze the Plasma Chambers Characteristics by 1/k Value Deduced From RF Parameters Collected by Impedance Meter

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2007.378958 ◽

2007 ◽

Author(s):

Kuo-Yen Chang ◽

Keh-Chyang Leou

Keyword(s):

K Value ◽

Impedance Meter

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[Front cover]

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2007.378891 ◽

2007 ◽

Keyword(s):

Front Cover

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A New Twin Flash™ Cell for 2 and 4 Bit Operation at 63nm Feature Size

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2007.378933 ◽

2007 ◽

Author(s):

N. Nagel ◽

H. Boubekeur ◽

F. Heinrichsdorff ◽

L. Bach ◽

V. Polei ◽

...

Keyword(s):

Feature Size

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Quantitative Evaluation of Line Width Roughness-Effect on Mosfet Electrical Properties Using a Large Array Test Structure

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) ◽

10.1109/vtsa.2007.378956 ◽

2007 ◽

Author(s):

Akira Shibuya ◽

Shigetaka Mori ◽

Takanori Kusakabe ◽

Yoshihisa Hiramatsu ◽

Nobuyuki Matsuzawa ◽

...

Keyword(s):

Electrical Properties ◽

Line Width ◽

Quantitative Evaluation ◽

Test Structure ◽

Large Array ◽

Roughness Effect

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2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

90nm Phase Change Technology with μTrench and Lance Cell Elements

Amorphization and Templated Recrystallization (ATR) Study for Hybrid Orientation Technology (HOT) using Direct Silicon Bond (DSB) Substrates

A Study on the Erase and Retention Mechanisms for MONOS, MANOS, and BE-SONOS Non-Volatile Memory Devices

Metrology and reliability of sub-45 nm Cu/ULK interconnects using multiline test structures

Monolithic 3D Integrated Circuits

Impact of advanced process modules and device architectures on the matching performance of (sub-)45nm CMOS

To Analyze the Plasma Chambers Characteristics by 1/k Value Deduced From RF Parameters Collected by Impedance Meter

[Front cover]

A New Twin Flash™ Cell for 2 and 4 Bit Operation at 63nm Feature Size

Quantitative Evaluation of Line Width Roughness-Effect on Mosfet Electrical Properties Using a Large Array Test Structure

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
Latest Publications