2017 IEEE Custom Integrated Circuits Conference (CICC)
Latest Publications

TOTAL DOCUMENTS

135

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781509051915

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

An 84 dB dynamic range 62.5–625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993655 ◽

2017 ◽

Cited By ~ 12

Author(s):

Masaya Miyahara ◽

Akira Matsuzawa

Keyword(s):

Dynamic Range ◽

Open Loop ◽

Sar Adc ◽

Noise Shaping

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A 4–40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993640 ◽

2017 ◽

Cited By ~ 5

Author(s):

Xuqiang Zheng ◽

Chun Zhang ◽

Fangxu Lv ◽

Feng Zhao ◽

Shigang Yue ◽

...

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A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993646 ◽

2017 ◽

Cited By ~ 1

Author(s):

Qiwei Wang ◽

Hajime Shibata ◽

Anthony Chan Carusone ◽

Antonio Liscidini

Keyword(s):

Front End ◽

Digitally Programmable ◽

Multi Band

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Digitally controlled voltage regulator using oscillator-based ADC with fast-transient-response and wide dropout range in 14nm CMOS

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993670 ◽

2017 ◽

Cited By ~ 2

Author(s):

Tarun Mahajan ◽

Ramnarayanan Muthukaruppan ◽

Dheeraj M. Shetty ◽

Sumedha Mangal ◽

Harish K. Krishnamurthy

Keyword(s):

Transient Response ◽

Voltage Regulator ◽

Fast Transient Response ◽

Digitally Controlled ◽

Fast Transient

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Session 11 — Wireline building blocks

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993602 ◽

2017 ◽

Author(s):

Eric Naviasky ◽

Mohammad Hekmat

Keyword(s):

Building Blocks

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A yield optimization methodology for mixed-signal circuits

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993682 ◽

2017 ◽

Cited By ~ 1

Author(s):

Aikaterini Papadopoulou ◽

Borivoje Nikolic

Keyword(s):

Yield Optimization ◽

Mixed Signal ◽

Mixed Signal Circuits ◽

Optimization Methodology

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Analog filter design: Current design techniques and trends

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993716 ◽

2017 ◽

Cited By ~ 1

Author(s):

Edgar Sanchez-Sinencio

Keyword(s):

Filter Design ◽

Analog Filter ◽

Current Design ◽

Design Techniques

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A pipelined SAR ADC reusing the comparator as residue amplifier

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993696 ◽

2017 ◽

Cited By ~ 7

Author(s):

Miguel Gandara ◽

Wenjuan Guo ◽

Xiyuan Tang ◽

Long Chen ◽

Yeonam Yoon ◽

...

Keyword(s):

Sar Adc

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Time-based ΑΣADCs

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993722 ◽

2017 ◽

Cited By ~ 1

Author(s):

Pavan Kumar Hanumolu

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Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs

2017 IEEE Custom Integrated Circuits Conference (CICC) ◽

10.1109/cicc.2017.7993678 ◽

2017 ◽

Cited By ~ 2

Author(s):

Eythan Familier ◽

Ian Galton

Keyword(s):

Low Noise ◽

Third Order ◽

Spurious Tone

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2017 IEEE Custom Integrated Circuits Conference (CICC)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

An 84 dB dynamic range 62.5–625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier

A 4–40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS

A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS

Digitally controlled voltage regulator using oscillator-based ADC with fast-transient-response and wide dropout range in 14nm CMOS

Session 11 — Wireline building blocks

A yield optimization methodology for mixed-signal circuits

Analog filter design: Current design techniques and trends

A pipelined SAR ADC reusing the comparator as residue amplifier

Time-based ΑΣADCs

Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs

2017 IEEE Custom Integrated Circuits Conference (CICC)
Latest Publications