Asymmetric and transient properties of reciprocal activity of antagonists during the paw-shake response in the cat

Mutually inhibitory populations of neurons, half-center oscillators (HCOs), are commonly involved in the dynamics of the central pattern generators (CPGs) driving various rhythmic movements. Previously, we developed a multifunctional, multistable symmetric HCO model which produced slow locomotor-like and fast paw-shake-like activity patterns. Here, we describe asymmetric features of paw-shake responses in a symmetric HCO model and test these predictions experimentally. We considered bursting properties of the two model half-centers during transient paw-shake-like responses to short perturbations during locomotor-like activity. We found that when a current pulse was applied during the spiking phase of one half-center, let’s call it #1, the consecutive burst durations (BDs) of that half-center increased throughout the paw-shake response, while BDs of the other half-center, let’s call it #2, only changed slightly. In contrast, the consecutive interburst intervals (IBIs) of half-center #1 changed little, while IBIs of half-center #2 increased. We demonstrated that this asymmetry between the half-centers depends on the phase of the locomotor-like rhythm at which the perturbation was applied. We suggest that the fast transient response reflects functional asymmetries of slow processes that underly the locomotor-like pattern; e.g., asymmetric levels of inactivation across the two half-centers for a slowly inactivating inward current. We compared model results with those of in-vivo paw-shake responses evoked in locomoting cats and found similar asymmetries. Electromyographic (EMG) BDs of anterior hindlimb muscles with flexor-related activity increased in consecutive paw-shake cycles, while BD of posterior muscles with extensor-related activity did not change, and vice versa for IBIs of anterior flexors and posterior extensors. We conclude that EMG activity patterns during paw-shaking are consistent with the proposed mechanism producing transient paw-shake-like bursting patterns found in our multistable HCO model. We suggest that the described asymmetry of paw-shaking responses could implicate a multifunctional CPG controlling both locomotion and paw-shaking.

Modified Predictive Control System of the DC-DC Boost Converter

Nowadays, predictive control systems are becoming more and more popular, which significantly reduce the cost of setting up converters. However, DC-DC converter control problem persists. In this work, a modified model of the predictive control system (MPCS) for step-up DC-DC converters is presented. For its implementation, a nonlinear model of a converter with discrete time switching was derived, which describe a continuous conduction mode of operation. The synthesis of the controller was achieved by formulating the objective function that should be minimized considering the dynamic model of the converter. The proposed predictive control strategy, used as a voltage control system, allows keeping the output voltage at the reference level. The modified system for calculating the objective function makes it possible to significantly reduce the required computing power and expand the prediction horizon. The results of modeling have been presented that demonstrate the advantages of the proposed control method: a fast transient response and a high degree of robustness.

A Hybrid-Mode LDO Regulator with Fast Transient Response Performance for IoT applications

A hybrid-mode low-drop out (LDO) voltage regulator with fast transient response performance for IoT applications is proposed in this paper. The proposed LDO regulator consist of two sections. First section is an analog regulator which includes a folded cascode operational amplifier to achieve good PSRR. Second section is current DAC and detectors whitch includes a cource current DAC, sink current DAC, undershoot detectors, and overshoot detectors. The current DAC and detectors are designed to obtain a low drop out and fast transient response. The proposed hybrid-mode LDO voltage regulator has been designed, simulated and layouted in Cadence using TSMC 90 nm CMOS technology. The input range of the LDO regulator is 1.2–2.0 V, and it can produces an output voltage of 1.2V. The LDO regulator achieves 58uA quiescent current, -69 PSRR @ 1 KHz noise frequency and an output voltage drop of around 60mV for a load current step of 100 mA. The final design occupies approximately 0.09 mm2.

Investigation of 2DOF PID Controller for Physio-Therapeutic Application for Elbow Rehabilitation

The aim of this work is to evaluate the output of a two-degree of freedom (DOF) proportional integral derivative (PID) controller for controlling elbow flexion and extension on an upper limb rehabilitation robot of an existing model. Since the usage of upper limb rehabilitation is increasing dramatically because of human impairment, 2DOF has been proposed in this work as a suitable controller. The 2DOF PID controller offers set-point-weight features and, hence, is fast in removing disturbance from the system and ensuring system stability. Importantly, as the system parameters are unknown in this work, the black-box model approach has been taken into consideration, using the MATLAB System identification toolbox to estimate a model. The best-fitted estimated model is then coupled with the proposed controller in the MATLAB/Simulink environment that, upon successful simulation works, leads, finally, to the hardware implementation. Three different amplitudes of sinusoidal current signals, such as 0.3 amps, 0.2 amps, and 0.1 amps, are applied for hardware measurements. Considering patients’ physical conditions. In this work, the 2DOF controller offers a fast transient response, settling time, negligible tracking error and 0% overshoot and undershoot.

Capacitor-less Low-Dropout Regulator for Analog Sensing using 90nm Technology

The capacitor-less-output-low-dropout (CLO-LDO) regulator proposed in this study can manage a wide variety of load currents. To offer temperature independent controlled LDO output, the LDO's 0.844V reference voltage is obtained using BGR, the optimized design is presented that provide full range stability, fast transient response. These benefits allow the proposed LDO regulator to operate over a wide range of operating circumstances, with very high current efficiency 99.99% and low voltage drop 100mV, operating using very low quiescent current of 0.02µA, at the output of regulator. The proposed regulator design is constructed in 90nm CMOS technology, the structure of the regulator is implemented using a Two-stage operational amplifier to obtain large DC gain 50dB to improve supply noise rejection, and a feedback loop, and exhibits better performance in terms of large phase margin 64.516 degrees with no load and 70.63degree full load.