Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs

2017 ◽  
Author(s):  
Eythan Familier ◽  
Ian Galton
Keyword(s):  
Low Noise ◽  
Third Order ◽  
Spurious Tone

scholarly journals Design of the Low Noise Amplifier Circuit in Band L for Improve the Gain and Circuit Stability

2018 ◽  
Vol 1 (4) ◽  
Author(s):  
Arash Omidi ◽  
Rohalah Karami ◽  
Parisa Sadat Emadi ◽  
Hamed Moradi
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
System Stability ◽  
Third Order ◽  
Cmos Transistor ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
The Cost ◽  
Intercept Point

In this paper, focuses on the design of Low Noise Amplifier circuitry in the frequency band L. This circuit is designed using the 0.18 nm CMOS transistor technology, which consists of two transistor Stage. The purpose of this research is to improve the cost of: Increase Gain - Increase circuit linearization - Create an integrative matching network for system stability. The application of this circuit can be used in wireless and GPS systems. The CMOS LNA exhibits a gain greater than 23 dB from 1.1 to 2.0 GHz, and a noise figure of 2.7 to 3.3 dB from 1.2 to 2.4 GHz. At 1.575 GHz, the 1-dB compression point (P1dB) is 1.73 dBm, with an input third-order intercept point (IIP3) of -3.98 dBm. This circuit is designed using ADS software.

scholarly journals Fully-Integrated Tunable Q-Enhanced Linear Low Noise Amplifier for Wireless Receivers

2020 ◽  
Vol 9 (3) ◽  
pp. 1762-1766
Keyword(s):  
Quality Factor ◽  
Tuning Range ◽  
Low Noise ◽  
Wireless Receivers ◽  
Center Frequency ◽  
Third Order ◽  
Fully Integrated ◽  
Noise Amplifier ◽  
Quality Factor Q ◽  
Peak Gain

This paper presents the design of a fully-integrated tunable Q-enhanced LNA resonator filter designed to tune the circuit center frequency and quality factor Q. The proposed circuit achieves a 600 MHz 3dB bandwidth tunable center frequency at 2.4 GHz with a 5.5 dB Quality Factor Q tuning range. The proposed circuit utilize a distortion transistor compensator to improve linearity of the circuit. The results show an 18 dBc of third order intermodulation IM3 cancellation. The overall proposed circuit peak gain is 16.5 dB and the minimum NF is 0.94 dB at 2.4 GHz frequency with power consumption of 5.2 mA

A 6.5-kV HBM ESD-protected high-gain LNA using cascaded L-match input network

2019 ◽  
Vol 33 (23) ◽  
pp. 1950280
Author(s):  
Guoxiao Cheng ◽  
Zhiqun Li ◽  
Pengfei Yue ◽  
Lei Luo ◽  
Xiaodong He ◽  
...  
Keyword(s):  
Noise Figure ◽  
Nonlinear Coefficient ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Third Order ◽  
Input Matching ◽  
Third Stage ◽  
Protection Circuits ◽  
Noise Amplifier

A wideband (2–3 GHz) three-stage low noise amplifier (LNA) with electrostatic discharge (ESD) protection circuits using 0.18 [Formula: see text]m CMOS technology is presented in this paper. Low-parasitic silicon-controlled rectifier (SCR) devices are co-designed with the LNA in the form of [Formula: see text]-parameters, and a new cascaded L-match input network is proposed to reduce the parasitic effects of them on the input matching. To improve linearity performance, an optimized multiple-gated transistors method (MGTR) is proposed and applied to the third stage, which takes both transconductance [Formula: see text] and third-order nonlinear coefficient [Formula: see text] into consideration. The measured results show a wide input matching across 2–8 GHz and a high third-order input intercept point (IIP3) of −12.8 dBm. The peak power gain can achieve 29.1 dB, and the noise figure (NF) is in a range of 3.1–3.6 dB within the 3-dB bandwidth. Using SCR devices with low parasitic capacitance of [Formula: see text]80 fF and robust gate-driven power clamps, a 6.5-kV human body mode (HBM) ESD performance is obtained.

A 0.1–1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

2018 ◽  
Vol 32 (02) ◽  
pp. 1850009 ◽  
Author(s):  
Benqing Guo ◽  
Jun Chen ◽  
Hongpeng Chen ◽  
Xuebing Wang
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Voltage Gain ◽  
Third Order ◽  
Weak Inversion ◽  
Linearization Technique ◽  
The Third ◽  
Noise Amplifier ◽  
Second Order Nonlinearity

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 [Formula: see text]m CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8–3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13–18.9 and 24–40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

Design of a WiMedia/MBOA 0.13μm CMOS Front-End

2012 ◽  
Vol 198-199 ◽  
pp. 1306-1312
Author(s):  
Hong Zhang ◽  
Yuan Liang
Keyword(s):  
Noise Figure ◽  
Data Communication ◽  
Direct Conversion ◽  
Low Noise ◽  
Ultra Wideband ◽  
Third Order ◽  
Front End ◽  
Single Sideband ◽  
Noise Amplifier ◽  
Better Than

This paper addresses the design of a 3.0-8.0GHz direct-conversion receiver front-end chip for ultra-wideband (UWB) WiMedia/MBOA data communication. It comprises a partial noise cancellation broadband low-noise amplifier (LNA) and a linearity enhancement quadrature mixer. The simulation results show that the chip performance achieved the input reflection coefficient better than -11dB along the entire band and a minimum single sideband noise figure (SSB NF) of 6.57dB at IF frequency of baseband. The conversion gain ranges from 24.9dB to 29.5dB while the input third order interception point (IIP3) ranges from 1.5dBm to 8.7dBm. The chip core merely consumes 20mW from 1.2V supply.

scholarly journals A Four-Channel CMOS Front-End for Interference-Robust GNSS Receiver

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 291
Author(s):  
Fang Han ◽  
Jian Gao ◽  
Xiaoran Li ◽  
Zhiming Chen
Keyword(s):  
Local Oscillator ◽  
Cmos Technology ◽  
Satellite System ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Third Order ◽  
Front End ◽  
Mixer Design ◽  
Linearity Improvement ◽  
Global Navigation Satellite

A four-channel receiver front-end is designed and implemented for interference- and jamming-robust global navigation satellite system (GNSS) in a 0.18-μm CMOS technology. The front-end consists of four identical RF-to-IF signal paths including low-noise amplifiers (LNAs), mixers and IF amplifiers. In addition, it also includes a phase-locked loop (PLL), which synthesizes the local oscillator (LO) signal, and a serial peripheral interface (SPI) for parameter adjustment. To improve the interference and jamming robustness, a novel linearity improvement technology and LO duty cycle adjustment method are applied in LNA and mixer design, respectively. The receiver achieves a gain of 40 dB, an input-referred third-order intercept point (IIP3) of −8 dBm and a jammer-to-signal power ratio (JSR) of 72 dB under 1.8-V and 3.3-V supply, while occupying a 4 × 5 mm2 die area including the electrostatic discharge (ESD) I/O pads.

scholarly journals Broadband GaAs pHemt LNA design for T/R module application

2016 ◽  
Vol 54 (5) ◽  
pp. 584
Author(s):  
Phong Dai Le ◽  
Vu Duy Thong ◽  
Pham Le Binh
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Small Signal Gain ◽  
Small Signal ◽  
Third Order ◽  
Wide Bandwidth ◽  
Fully Integrated ◽  
Three Stages ◽  
Noise Amplifier

In this paper, a three stages monolithic low noise amplifier (LNA) for T/R module application is presented. This LNA is fully integrated on 0.15-um pHEMT GaAs technology and achieves a wide bandwidth from 6 GHz to 11 GHz. Within this band, the LNA has the minimum of 1.3 dB noise figure and over 25 dB small signal gain. The output third order interception point (OIP3) is over 30 dBm and the 1 dB compression point (P1 dB) is 16 dBm at the output.

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