22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)
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0769528856, 9780769528854

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) ◽

10.1109/dft.2007.12 ◽

2007 ◽

Cited By ~ 2

Author(s):

Rani S. Ghaida ◽

Payman Zarkesh-Ha

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Committees

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) ◽

10.1109/dft.2007.6 ◽

2007 ◽

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Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) ◽

10.1109/dft.2007.27 ◽

2007 ◽

Author(s):

Somayyeh Koohi ◽

Shaahin Hessabi

Keyword(s):

Empirical Analysis ◽

Fault Coverage ◽

Test Power

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SET Emulation Under a Quantized Delay Model

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) ◽

10.1109/dft.2007.49 ◽

2007 ◽

Cited By ~ 7

Author(s):

Mario Garcia Valderas ◽

Raul Fernandez Cardenal ◽

Celia Lopez Ongil ◽

Marta Portela Garcia ◽

Luis Entrena

Keyword(s):

Delay Model

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Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) ◽

10.1109/dft.2007.61 ◽

2007 ◽

Cited By ~ 16

Author(s):

Francesco Regazzoni ◽

Thomas Eisenbarth ◽

Johann Grobschadl ◽

Luca Breveglieri ◽

Paolo Ienne ◽

...

Keyword(s):

Error Detection ◽

Power Attacks

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Optimization of Self Checking FIR filters by means of Fault Injection Analysis

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) ◽

10.1109/dft.2007.23 ◽

2007 ◽

Cited By ~ 1

Author(s):

S. Pontarelli ◽

L. Sterpone ◽

G.C. Cardarilli ◽

M. Re ◽

M. Sonza Reorda ◽

...

Keyword(s):

Fault Injection ◽

Fir Filters

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Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) ◽

10.1109/dft.2007.44 ◽

2007 ◽

Cited By ~ 1

Author(s):

Takashi IKEDA ◽

Kazuteru NAMBA ◽

Hideo ITO

Keyword(s):

Soft Error ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing

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A Defect-Tolerant Molecular-Based Memory Architecture

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) ◽

10.1109/dft.2007.22 ◽

2007 ◽

Cited By ~ 2

Author(s):

Yoon-hwa Choi ◽

Myeong-hyeon Lee

Keyword(s):

Memory Architecture

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Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) ◽

10.1109/dft.2007.42 ◽

2007 ◽

Cited By ~ 8

Author(s):

A. Matrosova ◽

E. Loukovnikova ◽

S. Ostanin ◽

A. Zinchuck ◽

E. Nikolaeva

Keyword(s):

Test Generation ◽

Combinational Circuit

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22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems - Table of Contents

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) ◽

10.1109/dft.2007.7 ◽

2007 ◽

Keyword(s):

Fault Tolerance ◽

International Symposium ◽

Ieee International Symposium

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22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model

Committees

Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs

SET Emulation Under a Quantized Delay Model

Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits

Optimization of Self Checking FIR filters by means of Fault Injection Analysis

Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing

A Defect-Tolerant Molecular-Based Memory Architecture

Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems - Table of Contents

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)
Latest Publications