HALF ADDER DESIGN USING VARIOUS TECHNOLOGIES AND COMPARISON OF

: In this paper, investigate and analysis various techniques for implementing a half adder circuit with the fewest transistors possible. In digital electronics half adder combinational circuit used to add two numbers. It is an arithmetic circuit that performs the arithmetic operation of adding two single-bit words. The half adder technique, design of half adder using AVL technology, Design of a 3-T Half Adder, NMOS pass transistors logic design of half adder using 2:1 MUX, half adder circuit design with CMOS NAND gates, half adder circuit design with CMOS transmission logic gates in cadence virtuoso. In this section, compare half adder circuit design techniques and compare various parameters of half adder circuit design used various circuit design techniques. Conventional techniques required fewer number routing resources. A 3-T halfadder circuit performs with less delay, high speed, small layout area, less power consumption and batter efficiency and accuracy

CoCEC: An Automatic Combinational Circuit Equivalence Checker Based on the Interactive Theorem Prover

Checking the equivalence of two Boolean functions, or combinational circuits modeled as Boolean functions, is often desired when reliable and correct hardware components are required. The most common approaches to equivalence checking are based on simulation and model checking, which are constrained due to the popular memory and state explosion problems. Furthermore, such tools are often not user-friendly, thereby making it tedious to check the equivalence of large formulas or circuits. An alternative is to use mathematical tools, called interactive theorem provers, to prove the equivalence of two circuits; however, this requires human effort and expertise to write multiple output functions and carry out interactive proof of their equivalence. In this paper, we (1) define two simple, one formal and the other informal, gate-level hardware description languages, (2) design and develop a formal automatic combinational circuit equivalence checker (CoCEC) tool, and (3) test and evaluate our tool. The tool CoCEC is based on human-assisted theorem prover Coq, yet it checks the equivalence of circuit descriptions purely automatically through a human-friendly user interface. It either returns a machine-readable proof (term) of circuits’ equivalence or a counterexample of their inequality. The interface enables users to enter or load two circuit descriptions written in an easy and natural style. It automatically proves, in few seconds, the equivalence of circuits with as many as 45 variables (3.5 × 10 13 states). CoCEC has a mathematical foundation, and it is reliable, quick, and easy to use. The tool is intended to be used by digital logic circuit designers, logicians, students, and faculty during the digital logic design course.

Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks

Logic locking has emerged as a promising solution to protect integrated circuits against piracy and tampering. However, the security provided by existing logic locking techniques is often thwarted by Boolean satisfiability (SAT)-based oracle-guided attacks. Criteria for successful SAT attacks on locked circuits include: (i) the circuit under attack is fully combinational, or (ii) the attacker has scan chain access. To address the threat posed by SAT-based attacks, we adopt the dynamically obfuscated scan chain (DOSC) architecture and illustrate its resiliency against the SAT attacks when inserted into the scan chain of an obfuscated design. We demonstrate, both mathematically and experimentally, that DOSC exponentially increases the resiliency against key extraction by SAT attack and its variants. Our results show that the mathematical estimation of attack complexity correlates to the experimental results with an accuracy of 95% or better. Along with the formal proof, we model DOSC architecture to its equivalent combinational circuit and perform SAT attack to evaluate its resiliency empirically. Our experiments demonstrate that SAT attack on DOSC-inserted benchmark circuits timeout at minimal test time overhead, and while DOSC requires less than 1% area and power overhead.

Overhead and Performance Comparison of SET Fault Tolerant Circuits Used in Flash-based FPGAs

The aim of alternative fault tolerant techniques used in flash-based FPGAs, such as Single Event Transient (SET) filters, is to provide a resource savings advantage when compared to Triple Modular Redundancy (TMR). The purpose of this paper is to quantify, in terms of particular circuit characteristics, what the savings will be. The results suggest that the most important circuit characteristic to determine the gate count increase is the ratio of the number of primary outputs to the original circuit gate count, when considering a combinational circuit. When considering a sequential circuit, the most important circuit characteristic is the ratio of the number of Register Logic (RL) vs. Combinational Logic (CL) in the datapath. The theoretical study found that the DMR and delay element Guard Gate (GG) SET filter technique used in sequential circuits, proved more costly than TMR in terms of resource increase, when the ratio of the number of RL vs. CL is greater than 10% and 28% respectively. Chip-level synthesis of circuits using these filter techniques with one family of flash-based FPGAs shows no gate count cost benefit compared to TMR when the ratio of the number of RL vs. CL is greater than 13% and 15% respectively.

APPLICATION OF MATRIX APPROACH OF FUZZY LOGIC FOR DECISION SUPPORT IN OIL MINING EQUIPMENT SERVICE

The work solves the problem of building an intelligent decision support system for servicing oil production equipment. At the first stage – the choice of an intelligent model – it is shown that in the existing conditions it is difficult to obtain a training sample in digital form. On the other hand, there is an opportunity to gain knowledge of subject matter experts – masters and technologists – in the form of a set of linguistic rules. Based on this, a conclusion about the effectiveness of the use of fuzzy logic to solve this problem is made. At the stage of constructing an intelligent model, the use of the matrix approach of fuzzy logic is proposed. To elaborate this approach an algorithm of fuzzy inference based on vector fuzzy predicates is developed. Capabilities and advantages of new algorithm are demonstrated. In particular, it is shown that the matrix representation makes possible reducing computations to solving a system of linear equations. Matrix inference also allows to explicitly determine the range of values of the analyzed parameters at which the knowledge base does not allow making a clear conclusion. A model of a fuzzy logic machine in the form of a fuzzy combinational circuit that analyzes an external memory block is proposed for the analysis of retrospective information on the change in the values of the parameters of technological equipment over time. Specific cases allowing the transition from a state machine to a combinational circuit are shown. Article also shows how this can be done. The main advantage of this approach is the absence of the need to use the difficult to formalize concept of a fuzzy state, which leads to a simplified construction of fuzzy logical devices with memory. At the end work contains brief conclusions about the application of the proposed methods and algorithms for building, testing, implementing a decision support system and about its effectiveness.

Design of multiplexing circuit using electro-optic effect based optical waveguides

The multiplexer is a combinational circuit that transfers multiple data inputs over a single output line. The input data are selected and transferred to the output line based on the selection line. In this work, 2 × 1 and 4 × 1 multiplexer is proposed. The proposed multiplexer has been worked out using the electro-optic principle. It is implemented using lithium niobate-based Mach–Zehnder interferometer (LN-MZI). LN-MZI is used as an optical switching device. The performance parameters extinction ratio, contrast ratio and insertion loss have been computed and found 31.31, 28.02 and 0.043 dB respectively.