Multichannel ADC IP Core on Xilinx SoC FPGA

Sensing of analogue signals such as voltage, temperature, pressure, current etc. is required to acquire the real time analog signals in the form digital streams. Most of the static analog signals are converted into voltage using sensors, transducers etc. and then measured using ADCs. The digitized samples from ADC are collected either through serial or parallel interface and processed by the programmable chips such as processors, controllers, FPGAs, SOCs etc. In some cases, Multichannel supported ADCs are used to save the layout area when the functionalities are to be realized in a small form factor. In such scenarios, parallel interface for each channel is not a preferred interface considering the more number of interfaces / traces between the components. Hence, Custom, Sink synchronized, Configurable multichannel ADC soft IP core has been developed using VHDL coding to interwork with multichannel supported, time division multiplexed ADCs with serial interface. The developed IP core can be used either as it is with the SPI interface as specified in this paper or with necessary modifications / configurations. The configurations can be the number of channels, sample size, sampling frequency, data transfer clock, type of synchronization – source / sink, control signals and the sequence of the operations performed to configure ADC. The efficiency of implementation is validated using the measurements of throughput, and accuracy for the required range of input with acceptable tolerances. ZYNQ FPGA and LTC2358 ADC are used to evaluate the developed IP core. Integrated Logic Analyser (ILA) which is an integrated verification tool of Vivado is used for Verification.

Investigating The Efficiency Of The VPR And COFFE Area Models In Predicting The Layout Area Of FPGA Lookup Tables

A single tile in a mesh-based FPGA includes both the routing block and the logic block. The area estimate of a tile in an FPGA is used to determine the physical length of an FPGA’s routing segments. An estimate of the physical length of the routing segments is needed in order to accurately assess the performance of a proposed FPGA architecture. The VPR (Versatile Place and Route) and the COFFE (Circuit Optimization for FPGA Exploration) tools are widely used meshbased FPGA exploration environments. These tools map, place, and route benchmark circuits on FPGA architectures. Subsequently, based on area and delay measurements, the best architectural parameters of an FPGA are decided. The area models of the VPR and COFEE tools take only transistor size as input to estimate the area of a circuit. Realistically, the layout area of a circuit depends on both the transistor size and the number of metal layers that are available to route the circuit. This work measures the effect of the number of metal layers that are available for routing on FPGA layout area through a series of carefully laid out 4-LUTs (4-input Lookup Tables). Based on measured results, a correction factor for the COFFE area equation is determined. The correction factor is a function of both the transistor drive strength and the number of metal layers that are available for routing. Consequently, a new area estimation equation, that is based on the COFFE area model, is determined. The proposed area equation takes into consideration the effect of both the transistor drive strength and the number of metal layers that are available for routing on layout area. The area prediction error of the proposed area equation is significantly less than the area prediction errors of the VPR and COFFE area models.

Investigating The Efficiency Of The VPR And COFFE Area Models In Predicting The Layout Area Of FPGA Lookup Tables

A single tile in a mesh-based FPGA includes both the routing block and the logic block. The area estimate of a tile in an FPGA is used to determine the physical length of an FPGA’s routing segments. An estimate of the physical length of the routing segments is needed in order to accurately assess the performance of a proposed FPGA architecture. The VPR (Versatile Place and Route) and the COFFE (Circuit Optimization for FPGA Exploration) tools are widely used meshbased FPGA exploration environments. These tools map, place, and route benchmark circuits on FPGA architectures. Subsequently, based on area and delay measurements, the best architectural parameters of an FPGA are decided. The area models of the VPR and COFEE tools take only transistor size as input to estimate the area of a circuit. Realistically, the layout area of a circuit depends on both the transistor size and the number of metal layers that are available to route the circuit. This work measures the effect of the number of metal layers that are available for routing on FPGA layout area through a series of carefully laid out 4-LUTs (4-input Lookup Tables). Based on measured results, a correction factor for the COFFE area equation is determined. The correction factor is a function of both the transistor drive strength and the number of metal layers that are available for routing. Consequently, a new area estimation equation, that is based on the COFFE area model, is determined. The proposed area equation takes into consideration the effect of both the transistor drive strength and the number of metal layers that are available for routing on layout area. The area prediction error of the proposed area equation is significantly less than the area prediction errors of the VPR and COFFE area models.

Design of JL-CFET(junctionless complementary field effect transistor)-based inverter for low power applications

Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (1) a high work function of metal gate and (2) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.

Compact and Energy Efficient Neuron With Tunable Spiking Frequency in 22-nm FDSOI

In this paper, we present a mixed-signal integrate and fire neuron designed in a 22-nm FDSOI technology. In this novel design, we deploy the back-gate terminal of FDSOI technology for a tunable design. For the first time, we show analytically and with pre- and post-layout simulations a neuron with tunable spiking frequency using the back-gate voltage of FDSOI technology. The neuron circuit is designed in the sub-threshold region and dissipates an ultra-low energy per spike of the order of Femto Joules per spike. With the layout area of only 30um^2, this is the smallest neuron circuit reported to date.

Compact and Energy Efficient Neuron With Tunable Spiking Frequency in 22-nm FDSOI

In this paper, we present a mixed-signal integrate and fire neuron designed in a 22-nm FDSOI technology. In this novel design, we deploy the back-gate terminal of FDSOI technology for a tunable design. For the first time, we show analytically and with pre- and post-layout simulations a neuron with tunable spiking frequency using the back-gate voltage of FDSOI technology. The neuron circuit is designed in the sub-threshold region and dissipates an ultra-low energy per spike of the order of Femto Joules per spike. With the layout area of only 30um^2, this is the smallest neuron circuit reported to date.

A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits

Single flux quantum (SFQ) logic is a promising technology to replace complementary metal-oxide-semiconductor logic for future exa-scale supercomputing but requires the development of reliable EDA tools that are tailored to the unique characteristics of SFQ circuits, including the need for active splitters to support fanout and clocked logic gates. This article is the first work to present a physical design methodology for inserting hold buffers in SFQ circuits. Our approach is variation-aware, uses common path pessimism removal and incremental placement to minimize the overhead of timing fixes, and can trade off layout area and timing yield. Compared to a previously proposed approach using fixed hold time margins, Monte Carlo simulations show that, averaging across 10 ISCAS’85 benchmark circuits, our proposed method can reduce the number of inserted hold buffers by 8.4% with a 6.2% improvement in timing yield and by 21.9% with a 1.7% improvement in timing yield.

Compact and Energy Efficient Neuron With Tunable Spiking Frequency in 22-nm FDSOI

<div>In this paper, we present an integrated and fire neuron designed in a 22-nm FDSOI technology. In this novel design, we deploy the back-gate terminal of FDSOI technology for a tunable design. For the first time, we show analytically and with pre- and post-layout simulations a neuron with tunable spiking frequency using the back-gate voltage of FDSOI technology. The neuron circuit is designed in the sub- hreshold region and dissipates an ultra-low energy per spike of the order of Femto Joules per spike. With the layout area of only 30 um2, this is the smallest neuron circuit reported to date.</div>

Compact and Energy Efficient Neuron With Tunable Spiking Frequency in 22-nm FDSOI

<div>In this paper, we present an integrated and fire neuron designed in a 22-nm FDSOI technology. In this novel design, we deploy the back-gate terminal of FDSOI technology for a tunable design. For the first time, we show analytically and with pre- and post-layout simulations a neuron with tunable spiking frequency using the back-gate voltage of FDSOI technology. The neuron circuit is designed in the sub- hreshold region and dissipates an ultra-low energy per spike of the order of Femto Joules per spike. With the layout area of only 30 um2, this is the smallest neuron circuit reported to date.</div>

HALF ADDER DESIGN USING VARIOUS TECHNOLOGIES AND COMPARISON OF

: In this paper, investigate and analysis various techniques for implementing a half adder circuit with the fewest transistors possible. In digital electronics half adder combinational circuit used to add two numbers. It is an arithmetic circuit that performs the arithmetic operation of adding two single-bit words. The half adder technique, design of half adder using AVL technology, Design of a 3-T Half Adder, NMOS pass transistors logic design of half adder using 2:1 MUX, half adder circuit design with CMOS NAND gates, half adder circuit design with CMOS transmission logic gates in cadence virtuoso. In this section, compare half adder circuit design techniques and compare various parameters of half adder circuit design used various circuit design techniques. Conventional techniques required fewer number routing resources. A 3-T halfadder circuit performs with less delay, high speed, small layout area, less power consumption and batter efficiency and accuracy