On the compact modelling of Si nanowire and Si nanosheet MOSFETs

In this paper, 3D TCAD simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in Nanowire and Nanosheet structures, are practically same. This characteristic makes possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend the application of the Symmetric Doped Double-Gate Model (SDDGM) model to Nanowires and Nanosheets MOSFETs, with no need to include new parameters. The Model SDDGM is validated for this application using several measured and simulated structures of Nanowires and Nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in SmartSPICE circuit simulator.

Systematic Design and Circuit Analysis of Lightning Impulse Voltage Generation on Low-Inductance Loads

The well-known circuit for the generation of lightning impulse voltage (LIV) on low-inductance loads was introduced by Glaninger in 1975, and the circuit component selection was proposed by Feser. However, the circuit and the approach for the component selection have some difficulties for which further adjustment is required for obtaining the waveform parameters according to the standard requirement. In this paper, an extended Glaninger’s circuit with an additional series resistor is proposed. Furthermore, a systematic design and circuit analysis of LIV generation for low-inductance loads are developed. With the help of a circuit simulator, the circuit analysis for the component selection is described. The validity of the proposed circuit was confirmed by some experimental results in comparison with the simulated ones. The proposed circuit and component selection provide not only the generation waveform according to the standard requirement but also other promising performances in terms of the wide inductance load range from 400 μH to 4 mH, a voltage efficiency of over 80%, an overshoot voltage of below 5%, an undershoot voltage of below 40%, and a maximum charging capacitance of 10 μF. From the simulated and experimental results, the proposed circuit and component selection approach is very useful for the LIV tests on low-inductance loads instead of using the conventional approach based on trial and error.

Smartphone Handwritten Circuits Solver Using Augmented Reality and Capsule Deep Networks for Engineering Education

Resolving circuit diagrams is a regular part of learning for school and university students from engineering backgrounds. Simulating circuits is usually done manually by creating circuit diagrams on circuit tools, which is a time-consuming and tedious process. We propose an innovative method of simulating circuits from hand-drawn diagrams using smartphones through an image recognition system. This method allows students to use their smartphones to capture images instead of creating circuit diagrams before simulation. Our contribution lies in building a circuit recognition system using a deep learning capsule networks algorithm. The developed system receives an image captured by a smartphone that undergoes preprocessing, region proposal, classification, and node detection to get a Netlist and exports it to a circuit simulator program for simulation. We aim to improve engineering education using smartphones by (1) achieving higher accuracy using less training data with capsule networks and (2) developing a comprehensive system that captures hand-drawn circuit diagrams and produces circuit simulation results. We use 400 samples per class and report an accuracy of 96% for stratified 5-fold cross-validation. Through testing, we identify the optimum distance for taking circuit images to be 10 to 20 cm. Our proposed model can identify components of different scales and rotations.

Qulacs: a fast and versatile quantum circuit simulator for research purpose

To explore the possibilities of a near-term intermediate-scale quantum algorithm and long-term fault-tolerant quantum computing, a fast and versatile quantum circuit simulator is needed. Here, we introduce Qulacs, a fast simulator for quantum circuits intended for research purpose. We show the main concepts of Qulacs, explain how to use its features via examples, describe numerical techniques to speed-up simulation, and demonstrate its performance with numerical benchmarks.

Stim: a fast stabilizer circuit simulator

This paper presents “Stim", a fast simulator for quantum stabilizer circuits. The paper explains how Stim works and compares it to existing tools. With no foreknowledge, Stim can analyze a distance 100 surface code circuit (20 thousand qubits, 8 million gates, 1 million measurements) in 15 seconds and then begin sampling full circuit shots at a rate of 1 kHz. Stim uses a stabilizer tableau representation, similar to Aaronson and Gottesman's CHP simulator, but with three main improvements. First, Stim improves the asymptotic complexity of deterministic measurement from quadratic to linear by tracking the inverse of the circuit's stabilizer tableau. Second, Stim improves the constant factors of the algorithm by using a cache-friendly data layout and 256 bit wide SIMD instructions. Third, Stim only uses expensive stabilizer tableau simulation to create an initial reference sample. Further samples are collected in bulk by using that sample as a reference for batches of Pauli frames propagating through the circuit.

Analysis of Narrow Slot Loading on a Half Guided Wavelength Folded Substrate Integrated Waveguide

In this paper, effects due to variation in positioning, width and length of a narrow slot loaded on central metal septum of a half guided wavelength Folded Substrate Integrated Waveguide (FSIW) segment is presented. The study shows that the most significant effect is due to variation in slot length. It was observed that the slot loading can be used both for slow wave structure and filter depending on the length of the slot. The smaller lengths of the slot provide the slow wave effect, whereas the longer lengths result in filtering effect. Both the phenomena are explained with the help of field diagrams for different propagating modes and extracted equivalent circuit for the Slot Loaded Folded Substrate Integrated Waveguide (SFSIW) segment. This study will help in deciding the dimensions of the slot as per application. The measured scattering parameters of the fabricated structure are compared with the simulated results obtained from the HFSS and the circuit simulator in ADS and are in good agreement.

Development of an Electrothermal Simulation Tool for Integrated Circuits

The goal of this research was to develop a capability for the electrothermal modeling of electronic circuits. The objective of the thermal modeling process was to create a model that represents the thermal behavior of the physical system. The project focuses on electrothermal analysis at devices and chip level. A novel method to perform electrothermal analysis of integrated circuits based on the relaxation approach is proposed in this research. An interface program couples a circuit simulator and a thermal simulator. The developed simulator is capable of performing both steady state and transient analaysis at devices and chip level. The proposed method was applied to perform electrothermal analysis of Silicon Bipolar Junction Transistor (BJT) to predict the temperature distribution and the device performance in a circuit. Thermal nonlinearity due to temperature-dependent material parameters in the context of thermal modeling of the device and circuit has also been considered. The DC characteristics of the device were investigated. The obtained results indicate that the operating point of the device varies while the device reaches its junction temperature. The accuracy of the electrothermal simulator has been evaluated for steady state analysis. The experimental results of a BJT amplifier were compared to the simulator results of the similar circuit. The electrothermal simulation results of BJT amplifier circuit indicate a good agreement with the available experimental results in terms of power dissipation, collector current and base-emitter voltage. The performance of the electrothermal simulator has been evaluated for tansient analysis. A current mirror circuit using Si NPN BJTs was simulated. According to the electrical simulator, the output current follows the reference current immediately. Nonetheless, the electrothermal simulator results depict that the load current has delay to reach a constant value which is not the same as the reference current, due to the influence of thermal coupling and self heating. The obtained results are in agreement with the available results in literature.

Development of an Electrothermal Simulation Tool for Integrated Circuits

The goal of this research was to develop a capability for the electrothermal modeling of electronic circuits. The objective of the thermal modeling process was to create a model that represents the thermal behavior of the physical system. The project focuses on electrothermal analysis at devices and chip level. A novel method to perform electrothermal analysis of integrated circuits based on the relaxation approach is proposed in this research. An interface program couples a circuit simulator and a thermal simulator. The developed simulator is capable of performing both steady state and transient analaysis at devices and chip level. The proposed method was applied to perform electrothermal analysis of Silicon Bipolar Junction Transistor (BJT) to predict the temperature distribution and the device performance in a circuit. Thermal nonlinearity due to temperature-dependent material parameters in the context of thermal modeling of the device and circuit has also been considered. The DC characteristics of the device were investigated. The obtained results indicate that the operating point of the device varies while the device reaches its junction temperature. The accuracy of the electrothermal simulator has been evaluated for steady state analysis. The experimental results of a BJT amplifier were compared to the simulator results of the similar circuit. The electrothermal simulation results of BJT amplifier circuit indicate a good agreement with the available experimental results in terms of power dissipation, collector current and base-emitter voltage. The performance of the electrothermal simulator has been evaluated for tansient analysis. A current mirror circuit using Si NPN BJTs was simulated. According to the electrical simulator, the output current follows the reference current immediately. Nonetheless, the electrothermal simulator results depict that the load current has delay to reach a constant value which is not the same as the reference current, due to the influence of thermal coupling and self heating. The obtained results are in agreement with the available results in literature.