2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)
Latest Publications

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9781538652916

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Towards novel format for representation of polymorphic circuits

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2018.8368583 ◽

2018 ◽

Cited By ~ 3

Author(s):

Adam Crha ◽

Vaclav Simek ◽

Richard Ruzicka

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An energy-autonomous wireless sensor network development platform

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2018.8368569 ◽

2018 ◽

Author(s):

Michelangelo Grosso ◽

Salvatore Rinaudo ◽

Edoardo Patti ◽

Andrea Acquaviva

Keyword(s):

Wireless Sensor Network ◽

Sensor Network ◽

Wireless Sensor ◽

Network Development ◽

Development Platform

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Analog fault simulation automation at schematic level with random sampling techniques

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2018.8368549 ◽

2018 ◽

Author(s):

Liang Wu ◽

Mohammad Khizer Hussain ◽

Saed Abughannam ◽

Wolfgang Muller ◽

Christoph Scheytt ◽

...

Keyword(s):

Random Sampling ◽

Fault Simulation ◽

Sampling Techniques ◽

Analog Fault Simulation

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[Blank page]

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2018.8368543 ◽

2018 ◽

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SIC pair generation in near-optimal time with carry-look ahead adders

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2018.8368573 ◽

2018 ◽

Author(s):

I. Voyiatzis ◽

C. Efstathiou

Keyword(s):

Optimal Time ◽

Look Ahead ◽

Pair Generation

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[Title page]

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2018.8368544 ◽

2018 ◽

Keyword(s):

Title Page

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Wireless sEMG/footswitch driven FPGA embedded digital processor for dynamic MFCV estimation

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2018.8368575 ◽

2018 ◽

Author(s):

Giovanni Mezzina ◽

Daniela De Venuto

Keyword(s):

Digital Processor

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Trading-off reliability and performance in FPGA-based reconfigurable heterogeneous systems

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2018.8368557 ◽

2018 ◽

Cited By ~ 2

Author(s):

Alessandro Vallero ◽

Alberto Carelli ◽

Stefano Di Carlo

Keyword(s):

Heterogeneous Systems ◽

And Performance

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The test cost reduction benefits of combining a hierarchical DFT methodology with EDT channel sharing — A case study

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2018.8368556 ◽

2018 ◽

Author(s):

Binghua Lu ◽

Selina Sha ◽

Jincheng Wang ◽

Zhigao Zhang ◽

Fanjin Meng ◽

...

Keyword(s):

Cost Reduction ◽

Test Cost ◽

Test Cost Reduction

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Impact of dynamic partial reconfiguration on CONNECT Network-on-Chip for FPGAs

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) ◽

10.1109/dtis.2018.8368587 ◽

2018 ◽

Author(s):

Ramy Ahmed ◽

Hassan Mostafa ◽

A. H. Khalil

Keyword(s):

Network On Chip ◽

Partial Reconfiguration ◽

Dynamic Partial Reconfiguration ◽

On Chip

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2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Towards novel format for representation of polymorphic circuits

An energy-autonomous wireless sensor network development platform

Analog fault simulation automation at schematic level with random sampling techniques

[Blank page]

SIC pair generation in near-optimal time with carry-look ahead adders

[Title page]

Wireless sEMG/footswitch driven FPGA embedded digital processor for dynamic MFCV estimation

Trading-off reliability and performance in FPGA-based reconfigurable heterogeneous systems

The test cost reduction benefits of combining a hierarchical DFT methodology with EDT channel sharing — A case study

Impact of dynamic partial reconfiguration on CONNECT Network-on-Chip for FPGAs

2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)
Latest Publications