Wideband Mixed Signal Separation Based on Photonic Signal Processing

The growing needs for high-speed and secure communications create an increasing challenge to the contemporary framework of signal processing. The coexistence of multiple high-speed wireless communication systems generates wideband interference. To protect the security and especially the privacy of users’ communications requires stealth communication that hides and recovers private information against eavesdropping attacks. The major problem in interference management and stealth information recovery is to separate the signal of interest from wideband interference/noise. However, the increasing signal bandwidth presents a real challenge to existing capabilities in separating the mixed signal and results in unacceptable latency. The photonic circuit processes a signal in an analog way with a unanimous frequency response over GHz bandwidth. The digital processor measures the statistical patterns of the signals with sampling rate orders of magnitude smaller than the Nyquist frequency. Under-sampling the signals significantly reduces the workload of the digital processor while providing accurate control of the photonic circuit to perform the real-time signal separations. The wideband mixed signal separation, based on photonic signal processing is scalable to multiple stages with the performance of each stage accrued.

SOGI-FLL Grid Frequency Monitoring with an Error-Based Algorithm for a Better Response in Face of Voltage Sag and Swell Faults

The SOGI-FLL (second-order generalized-integrator frequency-locked-loop) is a well-known and simple adaptive filter that allows estimation of the parameters of the grid voltage with a small computational burden. However, this structure has shown to be sensitive to the events of voltage sags and swell faults, especially to voltage sags that deeply distort the estimated frequency. In this paper an algorithm is proposed to face the fault that modifies the SOGI-FLLs gains in order to achieve a better transient response with a reduced perturbation in the estimated frequency. The algorithm uses the SOGI’s instantaneous and absolute error to detect the fault and change the SOGI-FLL gains during the fault. Moreover, the average of the absolute error is used for returning to normal operating conditions. The average value is obtained by means of a single low pass filter (LPF). The approach is easy to implement and represents a low computational burden for being implemented into a digital processor. The performance is evaluated by using simulations and real-time Typhoon Hardware in the Loop (HIL) results.

СБИС ЦИФРОВОГО ПРОЦЕССОРА ДЛЯ ФОРМИРОВАНИЯ И ОБРАБОТКИ ШУМОПОДОБНЫХ СИГНАЛОВ В СИСТЕМАХ СВЯЗИ НА БАЗЕ ЯДРА NMC3

В статье представлены результаты разработки СБИС цифрового процессора для формирования и обработки шумоподобных сигналов, используемого в системах связи класса «система на кристалле» на базе процессорного ядра NeuroMatrix® NMC3, ориентированного на векторно-матричную обработку потока данных произвольной разрядности. The paper describes the results of the development of a digital processor for generating and processing noise-like signals used in communication systems. The developed system-on-chip class processor is based on the NeuroMatrix® NMC3 processor core. NMC3 processor core has vector matrix architecture that is oriented to streaming data of variable bit width.

Accurate Detection of ECG Signals in ECG Monitoring Systems by Eliminating the Motion Artifacts and Improving the Signal Quality Using SSG Filter with DBE

The automatic recognition of QRS complexes in an Electrocardiography (ECG) signal is a critical step in any programmed ECG signal investigation, particularly when the ECG signal taken from the pregnant women additionally contains the signal of the fetus and some motion artifact signals. Separation of ECG signals of mother and fetus and investigation of the cardiac disorders of the mother are demanding tasks, since only one single device is utilized and it gets a blend of different heart beats. In order to resolve such problems we propose a design of new reconfigurable Subtractive Savitzky–Golay (SSG) filter with Digital Processor Back-end (DBE) in this paper. The separation of signals is done using Independent Component Analysis (ICA) algorithm and then the motion artifacts are removed from the extracted mother’s signal. The combinational use of SSG filter and DBE enhances the signal quality and helps in detecting the QRS complex from the ECG signal particularly the R peak accurately. The experimental results of ECG signal analysis show the importance of our proposed method.

Digital Fuzzy Current Mode Controlled Integrated PFC Converter with External Ramp Compensation

This paper propounded a novel method of design and realization of a digital fuzzy controlled buck integrated power factor correction (PFC) converter. It derives its advantages through the low buck capacitor voltage and single control switch (SW1), which leads to reduced complex control and price. Sub-harmonic oscillations generated in the peak current mode technique can be nullified by using the ramp signal, thereby improving the overall performance of the converter. The fuzzy logic controller (FLC) is robust and effective than the conventional linear controllers like P, PI, PID. In this paper, the digital fuzzy current mode controlled integrated PFC converter with external ramp compensation signal for 100 W load operating in the universal range of voltage (90[Formula: see text]V–265[Formula: see text]V), 50[Formula: see text]Hz has been designed and implemented using MATLAB/Simulink, verified in hardware using the TMS320F2812 digital processor board, and the results are found to be complying with international regulatory standards (IEC 6100-3-2 and IEEE 519-1992).