20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
Latest Publications

TOTAL DOCUMENTS

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE Comput. Soc

0769524648

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

On generating tests to cover diverse worst-case timing corners

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.50 ◽

2006 ◽

Cited By ~ 3

Author(s):

L. Lee ◽

S. Wu ◽

C.H.-P. Wen ◽

L.-C. Wang

Keyword(s):

Worst Case

Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.41 ◽

2006 ◽

Cited By ~ 22

Author(s):

L. Breveglieri ◽

I. Koren ◽

P. Maistri

Keyword(s):

Error Detection ◽

Advanced Encryption Standard

Data dependent jitter (DDJ) characterization methodology

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.25 ◽

2006 ◽

Cited By ~ 4

Author(s):

Kyung Ki Kim ◽

Yong-Bin Kim ◽

F. Lombardi

An integrated approach for increasing the soft-error detection capabilities in SoCs processors

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.17 ◽

2006 ◽

Cited By ~ 2

Author(s):

P. Bernardi ◽

L. Bolzani ◽

M. Rebaudengo ◽

M.S. Reorda ◽

M. Violante

Keyword(s):

Error Detection ◽

Integrated Approach ◽

Soft Error ◽

Detection Capabilities

Software-based self-test for pipelined processors: a case study

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.63 ◽

2006 ◽

Cited By ~ 3

Author(s):

M. Hatzimihail ◽

G. Xenoulis ◽

M. Psarakis ◽

D. Gizopoulos ◽

A. Paschalis

Keyword(s):

Self Test ◽

Pipelined Processors

A new test methodology for DNL error in flash ADCs

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.11 ◽

2006 ◽

Author(s):

M. Wieckowski ◽

J. Liobe ◽

Q. Diduck ◽

M. Margala

Keyword(s):

Test Methodology ◽

Flash Adcs

Design and analysis of self-repairable MEMS accelerometer

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.30 ◽

2006 ◽

Cited By ~ 9

Author(s):

Xingguo Xiong ◽

Yu-Liang Wu ◽

Wen-Ben Jone

Keyword(s):

Mems Accelerometer

QCA-based majority gate design under radius of effect-induced faults

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.55 ◽

2006 ◽

Cited By ~ 4

Author(s):

Z.D. Patitz ◽

N. Park ◽

Minsu Choi ◽

F.J. Meyer

Keyword(s):

Majority Gate ◽

Gate Design

Soft error modeling and protection for sequential elements

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.61 ◽

2006 ◽

Cited By ~ 17

Author(s):

H. Asadi ◽

M.B. Tahoori

Keyword(s):

Error Modeling ◽

Soft Error

A novel pulse echo correlation tool for transmission path testing and fault finding using pseudorandom binary sequences

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) ◽

10.1109/dftvs.2005.12 ◽

2006 ◽

Cited By ~ 3

Author(s):

D.M. Horan ◽

R.A. Guinee

Keyword(s):

Binary Sequences ◽

Transmission Path ◽

Path Testing ◽

Pulse Echo

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

On generating tests to cover diverse worst-case timing corners

Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard

Data dependent jitter (DDJ) characterization methodology

An integrated approach for increasing the soft-error detection capabilities in SoCs processors

Software-based self-test for pipelined processors: a case study

A new test methodology for DNL error in flash ADCs

Design and analysis of self-repairable MEMS accelerometer

QCA-based majority gate design under radius of effect-induced faults

Soft error modeling and protection for sequential elements

A novel pulse echo correlation tool for transmission path testing and fault finding using pseudorandom binary sequences

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
Latest Publications