High Accuracy Two-Step Flash ADC with Changeable Comparison Range Using Latch Based Comparator

Due to the technology development and decreasing supply voltages, undesirable effects on sensitive analog signals like noise, kickback are becoming more expressed. Mentioned issues are present in analog to digital converters (ADC) and design of high accuracy ADCs is becoming more complex. In this work, a circuit was proposed based on a latch comparator and comparison range shifter, which increased the accuracy of a two-step flash ADCs by excluding the chance of incorrect coarse conversion, when the input analog voltage is close to separating points of the comparison range of first stage of the ADC. The proposed circuit was constructed using an 16nm FinFET process, the simulations were done with HSpice simulator. The idea was to increase the accuracy of an already designed two-step flash ADC by adding the proposed circuit, which was done by shifting the comparison range during the coarse conversion, for the difference of input voltage and separating points not to be smaller than the offset of comparators used in ADC. It was established that the use of the proposed circuit increased the comparison time, as the sampled input analog voltage firstly should be compared with comparison range separating points, but on the other hand the ADC became more sensitive to its input change (up to 4mV offset) and was performing stable, excluding the chance of wrong coarse conversion. It has been shown that proposed architecture allows avoiding the use of low offset and high accuracy complex comparators in two-step flash ADCs, which greatly reduces the layout area.

Improvement of Gray ROM-Based Encoder for Flash ADCs

In this paper, gray ROM-based encoder is proposed for the implementation of flash ADCs encoder block based on converting the conventional 1-of-[Formula: see text] thermometer codes to 2-of-[Formula: see text] codes ([Formula: see text]). The proposed gray ROM-based encoder is composed of three stages. In the first stage, the thermometer codes are converted to 2-of-[Formula: see text] codes by the use of two-input AND and four-input merged AND–OR gates. In the second stage, 2-of-[Formula: see text] codes are turned to [Formula: see text] gray codes and a binary code by a quasi-gray ROM encoder and a binary ROM encoder, respectively. Finally, in the third stage, [Formula: see text] MSB bits and LSB bit are determined by a quasi-gray-to-binary converter and a CMOS inverter, respectively. The advantages of the proposed encoder over the conventional encoder are higher speed of second stage, low power, low area and low latency with the same bubble and meta-stability errors removing capability. To demonstrate the mentioned specifications, two 5-bit flash ADCs with the conventional and proposed encoders in their encoder blocks are analyzed and simulated at 2-GS/s and 3.2-GS/s sampling rates in 0.18-[Formula: see text]m CMOS process. Simulation results show that the ENOBs of flash ADCs with the conventional and proposed encoders are equal. In this case, the proposed encoder outputs are determined to be approximately 30[Formula: see text]ps faster than the conventional encoder at 2 GS/s. The power dissipations of the conventional and proposed encoders were 19.50[Formula: see text]mW and 13.90[Formula: see text]mW at 3.2-GS/s sampling rate from a 1.8-V supply and also the latencies of the encoders were 4 ADC clocks and 3 ADC clocks, respectively. In this case, the number of D-FFs and logic gates of the proposed encoder is decreased approximately by 37% when compared to the conventional encoder.