An integrated approach for increasing the soft-error detection capabilities in SoCs processors

2006 ◽  
Author(s):  
P. Bernardi ◽  
L. Bolzani ◽  
M. Rebaudengo ◽  
M.S. Reorda ◽  
M. Violante
Keyword(s):  
Error Detection ◽  
Integrated Approach ◽  
Soft Error ◽  
Detection Capabilities

scholarly journals Optimized switch-level soft error detection based on advanced switch-level models

2021 ◽  
Author(s):  
Jalal Mohammad Chikhe
Keyword(s):  
Error Detection ◽  
Early Stage ◽  
Soft Errors ◽  
Logic Gate ◽  
Soft Error ◽  
Combinational Circuits ◽  
Single Event Transient ◽  
New Techniques ◽  
Speed Up ◽  
Logic Threshold

Due to the reduction of transistor size, modern circuits are becoming more sensitive to soft errors. The development of new techniques and algorithms targeting soft error detection are important as they allow designers to evaluate the weaknesses of the circuits at an early stage of the design. The project presents an optimized implementation of soft error detection simulator targeting combinational circuits. The developed simulator uses advanced switch level models allowing the injection of soft errors caused by single event-transient pulses with magnitudes lesser than the logic threshold. The ISCAS'85 benchmark circuits are used for the simulations. The transients can be injected at drain, gate, or inputs of logic gate. This gives clear indication of the importance of transient injection location on the fault coverage. Furthermore, an algorithm is designed and implemented in this work to increase the performance of the simulator. This optimized version of the simulator achieved an average speed-up of 310 compared to the non-algorithm based version of the simulator.

A Novel Optimum Data Duplication Approach for Soft Error Detection

2008 ◽  
Author(s):  
Jianjun Xu ◽  
Qingping Tan ◽  
Rui Shen
Keyword(s):  
Error Detection ◽  
Soft Error

Performance Characteristics of Several Rules for Self-interpretation of Proficiency Testing Data

2005 ◽  
Vol 129 (8) ◽  
pp. 997-1003 ◽  
Author(s):  
R. Neill Carey ◽  
George S. Cembrowski ◽  
Carl C. Garber ◽  
Zohreh Zaki
Keyword(s):  
Proficiency Testing ◽  
Error Detection ◽  
Clinical Laboratory ◽  
Peer Group ◽  
Simulation Techniques ◽  
Allowable Error ◽  
Detection Capabilities ◽  
The Mean ◽  
The Difference

Abstract Context.—Proficiency testing (PT) participants can interpret their results to detect errors even when their performance is acceptable according to the limits set by the PT provider. Objective.—To determine which rules for interpreting PT data provide optimal performance for PT with 5 samples per event. Design.—We used Monte Carlo computer simulation techniques to study the performance of several rules, relating their error detection capabilities to (1) the analytic quality of the method, (2) the probability of failing PT, and (3) the ratio of the peer group SD to the mean intralaboratory SD. Analytic quality is indicated by the ratio of the PT allowable error to the intralaboratory SD. Failure of PT was defined (Clinical Laboratory Improvement Amendments of 1988) as an event when 2 or more results out of 5 exceeded acceptable limits. We investigated rules with limits based on the SD index, the mean SD index, and percentages of allowable error. Results.—No single rule performs optimally across the range of method quality. Conclusions.—We recommend further investigation when PT data cause rejection by any of the following 3 rules: any result exceeds 75% of allowable error, the difference between any 2 results exceeds 4 times the peer group SD, or the mean SD index of all 5 results exceeds 1.5. As method quality increases from marginal to high, false rejections range from 16% to nearly zero, and the probability of detecting a shift equal to 2 times the intralaboratory SD ranges from 94% to 69%.

Identification of Critical Variables for Soft Error Detection

2016 ◽  
pp. 310-321 ◽  
Author(s):  
Junchi Ma ◽  
Yun Wang
Keyword(s):  
Error Detection ◽  
Soft Error

Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC

2017 ◽  
pp. 189-201 ◽  
Author(s):  
Ádria Barros de Oliveira ◽  
Lucas Antunes Tambara ◽  
Fernanda Lima Kastensmidt
Keyword(s):  
Error Detection ◽  
Soft Error ◽  
Dual Core

Xentry: Hypervisor-Level Soft Error Detection

2014 ◽  
Author(s):  
Xin Xu ◽  
Ron C. Chiang ◽  
H. Howie Huang
Keyword(s):  
Error Detection ◽  
Soft Error

Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution

2011 ◽  
Vol 60 (10) ◽  
pp. 1511-1516 ◽  
Author(s):  
Pedro Reviriego ◽  
Chris Bleakley ◽  
Juan Antonio Maestro ◽  
Anne O'Donnell
Keyword(s):  
Error Detection ◽  
Soft Error ◽  
Correction Technique ◽  
Error Detection And Correction
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