1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)
Latest Publications

TOTAL DOCUMENTS

173

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0780351266

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Low-skew clock generator with dynamic impedance and delay matching

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759183 ◽

2003 ◽

Cited By ~ 2

Author(s):

A. Balatsos ◽

D. Lewis

Keyword(s):

Clock Generator ◽

Dynamic Impedance

10 mW CMOS retina and classifier for handheld, 1000 images/s optical character recognition system

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759194 ◽

2003 ◽

Author(s):

P. Masa ◽

P. Heim ◽

E. Franzi ◽

X. Arreguit ◽

F. Heitger ◽

...

Keyword(s):

Character Recognition ◽

Optical Character Recognition ◽

Recognition System ◽

Optical Character

A 1 Gb/s CMOS clock and data recovery circuit

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759292 ◽

2003 ◽

Author(s):

Hui Wang ◽

R. Nottenburg

Keyword(s):

Clock And Data Recovery ◽

Data Recovery

A versatile 3.3 V/2.5 V/1.8 V CMOS I/O driver built in a 0.2 μm 3.5 nm Tox 1.8 V CMOS technology

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759244 ◽

2003 ◽

Cited By ~ 1

Author(s):

H. Sanchez ◽

J. Siegel ◽

C. Nicoletta ◽

J. Alvarez ◽

J. Nissen ◽

...

Keyword(s):

Cmos Technology

A 2.5 Gb/s adaptive cable equalizer

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759317 ◽

2003 ◽

Cited By ~ 14

Author(s):

M.H. Shakiba

A 6.5 GHz monolithic CMOS voltage-controlled oscillator

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759323 ◽

2003 ◽

Cited By ~ 3

Author(s):

Ting-Ping Liu

Keyword(s):

Voltage Controlled Oscillator

A 29mm/sup 2/ 1.8 V-only 16 Mb DINOR flash memory with gate-protected poly-diode (GPPD) charge pump

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759158 ◽

2003 ◽

Author(s):

M. Mihara ◽

Y. Miyawaki ◽

O. Ishizaki ◽

T. Hayasaka ◽

K. Kobayashi ◽

...

Keyword(s):

Flash Memory ◽

Charge Pump

450 MHz PowerPC/sup TM/ microprocessor with enhanced instruction set and copper interconnect

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759141 ◽

2003 ◽

Cited By ~ 9

Author(s):

J. Alvarez ◽

E. Barkin ◽

Chai-Chin Chao ◽

B. Johnson ◽

M. D'Addeo ◽

...

Keyword(s):

Instruction Set ◽

Copper Interconnect

A 1.4 ns access 700 MHz 288 kb SRAM macro with expandable architecture

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759188 ◽

2003 ◽

Cited By ~ 8

Author(s):

H. Shimizu ◽

K. Ijitsu ◽

H. Akiyoshi ◽

K. Aoyama ◽

H. Takatsuka ◽

...

A 390 mm/sup 2/ 16-bank 1 Gb DDR SDRAM with hybrid bitline architecture

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759336 ◽

2003 ◽

Author(s):

T. Kirihata ◽

G. Mueller ◽

B. Ji ◽

G. Frankowsky ◽

J. Ross ◽

...

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Low-skew clock generator with dynamic impedance and delay matching

10 mW CMOS retina and classifier for handheld, 1000 images/s optical character recognition system

A 1 Gb/s CMOS clock and data recovery circuit

A versatile 3.3 V/2.5 V/1.8 V CMOS I/O driver built in a 0.2 μm 3.5 nm Tox 1.8 V CMOS technology

A 2.5 Gb/s adaptive cable equalizer

A 6.5 GHz monolithic CMOS voltage-controlled oscillator

A 29mm/sup 2/ 1.8 V-only 16 Mb DINOR flash memory with gate-protected poly-diode (GPPD) charge pump

450 MHz PowerPC/sup TM/ microprocessor with enhanced instruction set and copper interconnect

A 1.4 ns access 700 MHz 288 kb SRAM macro with expandable architecture

A 390 mm/sup 2/ 16-bank 1 Gb DDR SDRAM with hybrid bitline architecture

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)
Latest Publications