Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn)
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A hierarchical framework to enhance scalability and performance of scheduling and mapping algorithms

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2014.6850384 ◽

2014 ◽

Author(s):

Wei Tang ◽

Forrest Brewer

Keyword(s):

Mapping Algorithms ◽

Hierarchical Framework ◽

And Performance

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Machine-learning based simulated annealer method for high level synthesis design space exploration

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2014.6850383 ◽

2014 ◽

Cited By ~ 10

Author(s):

Anushree Mahapatra ◽

Benjamin Carrion Schafer

Keyword(s):

Machine Learning ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

High Level Synthesis ◽

Synthesis Design ◽

High Level

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[Title page]

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2014.6850374 ◽

2014 ◽

Keyword(s):

Title Page

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Session 4: System-level synthesis

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2014.6850385 ◽

2014 ◽

Keyword(s):

System Level

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Session 2: Work-in-progress

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2014.6850380 ◽

2014 ◽

Keyword(s):

Work In Progress

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Accelerating full-system simulation and app analysis through focused multi-granularity profiling

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2014.6850378 ◽

2014 ◽

Cited By ~ 1

Author(s):

Tzu-Hsiang Su ◽

Wei-Shan Wu ◽

Chen-Te Chou ◽

Yuan-Chun Cheng ◽

Meng-Ting Tsai ◽

...

Keyword(s):

System Simulation ◽

Full System

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Considering variation and aging in a full chip design methodology at system level

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2014.6850386 ◽

2014 ◽

Cited By ~ 1

Author(s):

Domenik Helms ◽

Kim Gruttner ◽

Reef Eilers ◽

Malte Metzdorf ◽

Kai Hylla ◽

...

Keyword(s):

Design Methodology ◽

System Level ◽

Chip Design

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Precise deadlock detection for polychronous data-flow specifications

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2014.6850379 ◽

2014 ◽

Cited By ~ 2

Author(s):

Van Chan Ngo ◽

Jean-Pierre Talpin ◽

Thierry Gautier

Keyword(s):

Data Flow ◽

Deadlock Detection

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Session 3: High-level synthesis

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2014.6850382 ◽

2014 ◽

Keyword(s):

High Level Synthesis ◽

High Level

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A memory-first language and model for hardware-software cosynthesis

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn) ◽

10.1109/eslsyn.2014.6850381 ◽

2014 ◽

Author(s):

Kunal Arya ◽

Forrest Brewer

Keyword(s):

First Language

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Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A hierarchical framework to enhance scalability and performance of scheduling and mapping algorithms

Machine-learning based simulated annealer method for high level synthesis design space exploration

[Title page]

Session 4: System-level synthesis

Session 2: Work-in-progress

Accelerating full-system simulation and app analysis through focused multi-granularity profiling

Considering variation and aging in a full chip design methodology at system level

Precise deadlock detection for polychronous data-flow specifications

Session 3: High-level synthesis

A memory-first language and model for hardware-software cosynthesis

Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn)
Latest Publications