Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
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9

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1

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Published By Springer International Publishing

9783319023779, 9783319023786

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Pre-bond Scan Test Through TSV Probing

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs ◽

10.1007/978-3-319-02378-6_5 ◽

2013 ◽

pp. 115-135

Author(s):

Brandon Noia ◽

Krishnendu Chakrabarty

Keyword(s):

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Pre-bond TSV Test Through TSV Probing

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs ◽

10.1007/978-3-319-02378-6_4 ◽

2013 ◽

pp. 81-113 ◽

Author(s):

Brandon Noia ◽

Krishnendu Chakrabarty

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Test-Architecture Optimization and Test Scheduling

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs ◽

10.1007/978-3-319-02378-6_8 ◽

2013 ◽

pp. 181-237

Author(s):

Brandon Noia ◽

Krishnendu Chakrabarty

Keyword(s):

Test Scheduling ◽

Architecture Optimization ◽

Test Architecture

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Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs ◽

10.1007/978-3-319-02378-6_6 ◽

2013 ◽

pp. 137-158

Author(s):

Brandon Noia ◽

Krishnendu Chakrabarty

Keyword(s):

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Built-In Self-Test for TSVs

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs ◽

10.1007/978-3-319-02378-6_3 ◽

2013 ◽

pp. 55-79

Author(s):

Brandon Noia ◽

Krishnendu Chakrabarty

Keyword(s):

Self Test ◽

Built In Self Test

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Wafer Stacking and 3D Memory Test

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs ◽

10.1007/978-3-319-02378-6_2 ◽

2013 ◽

pp. 11-54

Author(s):

Brandon Noia ◽

Krishnendu Chakrabarty

Keyword(s):

Memory Test ◽

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Introduction

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs ◽

10.1007/978-3-319-02378-6_1 ◽

2013 ◽

pp. 1-10

Author(s):

Brandon Noia ◽

Krishnendu Chakrabarty

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Conclusions

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs ◽

10.1007/978-3-319-02378-6_9 ◽

2013 ◽

pp. 239-240

Author(s):

Brandon Noia ◽

Krishnendu Chakrabarty

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Post-Bond Test Wrappers and Emerging Test Standards

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs ◽

10.1007/978-3-319-02378-6_7 ◽

2013 ◽

pp. 159-180

Author(s):

Brandon Noia ◽

Krishnendu Chakrabarty

Keyword(s):

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