Built-In Self-Test for TSVs

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs ◽

10.1007/978-3-319-02378-6_3 ◽

2013 ◽

pp. 55-79

Author(s):

Brandon Noia ◽

Krishnendu Chakrabarty

Keyword(s):

Self Test ◽

Built In Self Test

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Test the S27 Benchmark Circuit by Using Built In Self Test and Test Pattern Generation

International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering ◽

10.15662/ijareeie.2014.0308083 ◽

2014 ◽

Vol 03 (08) ◽

pp. 11487-11495

Author(s):

S. Nagaraju ◽

Ch.N.L. Sujatha ◽

J.S.S. Ramaraju

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Benchmark Circuit ◽

Self Test ◽

Built In Self Test

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Memory Implementation in a System on Chip with Built-in Self-Test and Recovery Tools

Proceedings of Universities ELECTRONICS ◽

10.24151/1561-5405-2019-24-3-239-247 ◽

2019 ◽

Vol 24 (3) ◽

pp. 239-247

Author(s):

Vladimir G. Ryabtsev ◽

◽

Sergey V. Volobuev ◽

Keyword(s):

System On Chip ◽

Self Test ◽

Built In Self Test ◽

On Chip ◽

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RF Phase Error Built-In-Self-Test for A GSM SOC

i-manager’s Journal on Electrical Engineering ◽

10.26634/jee.1.4.378 ◽

2008 ◽

Vol 1 (4) ◽

pp. 39-44

Author(s):

Dallas Webster ◽

Loi Phan ◽

Oren Eliezer ◽

Rick Hudgens ◽

Donald Lie

Keyword(s):

Phase Error ◽

Self Test ◽

Built In Self Test

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Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/3427911 ◽

2021 ◽

Vol 26 (3) ◽

pp. 1-18

Author(s):

Mehmet Ince ◽

Ender Yilmaz ◽

Wei Fu ◽

Joonsung Park ◽

Krishnaswamy Nagaraj ◽

...

Keyword(s):

Phase Locked Loops ◽

Test And Evaluation ◽

Self Test ◽

Built In Self Test

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IBIST/sup TM/ (interconnect built-in self-test) architecture and methodology for pci express: intel's next-generation test and validation methodology for performance IO

International Test Conference, 2003. Proceedings. ITC 2003. ◽

10.1109/test.2003.1270909 ◽

2004 ◽

Author(s):

J.J. Nejedlo

Keyword(s):

Next Generation ◽

Pci Express ◽

Self Test ◽

Built In Self Test ◽

Test Architecture ◽

Generation Test

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Built-in-self-test 3-D ring oscillator for stacked 3DIC

2014 IEEE International Symposium on Radio-Frequency Integration Technology ◽

10.1109/rfit.2014.6933251 ◽

2014 ◽

Author(s):

Cheng Jin ◽

Ni Wang ◽

Xiaowen Xu ◽

Houjun Sun

Keyword(s):

Ring Oscillator ◽

Self Test ◽

Built In Self Test

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Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

2011 Design, Automation & Test in Europe ◽

10.1109/date.2011.5763109 ◽

2011 ◽

Author(s):

A Strano ◽

C Gómez ◽

D Ludovici ◽

M Favalli ◽

M E Gómez ◽

...

Keyword(s):

Network On Chip ◽

Structural Redundancy ◽

Self Test ◽

Built In Self Test ◽

On Chip ◽

Test Architecture

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A 2-15 GHz built-in-self-test system for wide-band phased arrays using self-correcting 8-state I/Q mixers

2016 IEEE MTT-S International Microwave Symposium (IMS) ◽

10.1109/mwsym.2016.7540430 ◽

2016 ◽

Author(s):

Tumay Kanar ◽

Gabriel M. Rebeiz

Keyword(s):

Phased Arrays ◽

Wide Band ◽

Test System ◽

Self Test ◽

Built In Self Test

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Run-Time Reconfigurable Built-in-Self-Test

2006 Canadian Conference on Electrical and Computer Engineering ◽

10.1109/ccece.2006.277610 ◽

2006 ◽

Author(s):

Rami Abielmona ◽

Voicu Groza ◽

Arkan Khalaf

Keyword(s):

Self Test ◽

Run Time ◽

Built In Self Test

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Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling

Journal of Electronic Testing ◽

10.1007/bf00135230 ◽

1991 ◽

Vol 2 (4) ◽

pp. 351-372 ◽

Author(s):

Abhijit Chatterjee ◽

Jacob A. Abraham

Keyword(s):

Test Generation ◽

Design For Testability ◽

Graph Labeling ◽

Self Test ◽

Arithmetic Units ◽

Built In Self Test

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