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Test-Architecture Optimization and Test Scheduling
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
◽
10.1007/978-3-319-02378-6_8
◽
2013
◽
pp. 181-237
Author(s):
Brandon Noia
◽
Krishnendu Chakrabarty
Keyword(s):
Test Scheduling
◽
Architecture Optimization
◽
Test Architecture
Download Full-text
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Test-architecture optimization and test scheduling for SOCs with core-level expansion of compressed test patterns
2008 Design, Automation and Test in Europe
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10.1145/1403375.1403422
◽
2008
◽
Author(s):
Anders Larsson
◽
Erik Larsson
◽
Krishnendu Chakrabarty
◽
Petru Eles
◽
Zebo Peng
Keyword(s):
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◽
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Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
2008 Design, Automation and Test in Europe
◽
10.1109/date.2008.4484684
◽
2008
◽
Cited By ~ 15
Author(s):
Anders Larsson
◽
Erik Larsson
◽
Krishnendu Chakrabarty
◽
Petru Eles
◽
Zebo Peng
Keyword(s):
Core Level
◽
Test Scheduling
◽
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Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/tcad.2011.2160177
◽
2011
◽
Vol 30
(11)
◽
pp. 1705-1718
◽
Cited By ~ 45
Author(s):
B. Noia
◽
K. Chakrabarty
◽
S. K. Goel
◽
E. J. Marinissen
◽
J. Verbree
Keyword(s):
Test Scheduling
◽
Architecture Optimization
◽
Test Architecture
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Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
◽
10.1109/tvlsi.2011.2160410
◽
2012
◽
Vol 20
(9)
◽
pp. 1621-1633
◽
Cited By ~ 14
Author(s):
Li Jiang
◽
Qiang Xu
◽
K. Chakrabarty
◽
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Keyword(s):
Test Scheduling
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Architecture Optimization
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Test Architecture
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Test Architecture Optimization for Post-bond Test and Pre-bond Tests of 3D SoCs Using TAM Reuse
IETE Journal of Research
◽
10.1080/03772063.2020.1870873
◽
2021
◽
pp. 1-11
Author(s):
Surajit Kumar Roy
◽
Chandan Giri
Keyword(s):
Architecture Optimization
◽
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Reconfigured test architecture optimization for TSV-based three-dimensional SoCs
IEICE Electronics Express
◽
10.1587/elex.11.20140661
◽
2014
◽
Vol 11
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◽
pp. 20140661-20140661
◽
Cited By ~ 1
Author(s):
Kele Shen
◽
Dong Xiang
◽
Zhou Jiang
Keyword(s):
Three Dimensional
◽
Architecture Optimization
◽
Test Architecture
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SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects
2007 44th ACM/IEEE Design Automation Conference
◽
10.1109/dac.2007.375250
◽
2007
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Author(s):
Qiang Xu
◽
Yubin Zhang
◽
Krishnendu Chakrabarty
Keyword(s):
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◽
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◽
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SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects
ACM Transactions on Design Automation of Electronic Systems
◽
10.1145/1455229.1455233
◽
2009
◽
Vol 14
(1)
◽
pp. 1-27
◽
Cited By ~ 5
Author(s):
Qiang Xu
◽
Yubin Zhang
◽
Krishnendu Chakrabarty
Keyword(s):
Signal Integrity
◽
Soc Test
◽
Embedded Cores
◽
Architecture Optimization
◽
Test Architecture
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SOC test architecture optimization for signal integrity faults on core-external interconnects
2007 44th ACM/IEEE Design Automation Conference
◽
10.1145/1278480.1278651
◽
2007
◽
Author(s):
Qiang Xu
◽
Yubin Zhang
◽
Krishnendu Chakrabarty
Keyword(s):
Signal Integrity
◽
Soc Test
◽
Architecture Optimization
◽
Test Architecture
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Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs
2016 IEEE 25th Asian Test Symposium (ATS)
◽
10.1109/ats.2016.42
◽
2016
◽
Cited By ~ 3
Author(s):
Shengcheng Wang
◽
Ran Wang
◽
Krishnendu Chakrabarty
◽
Mehdi B. Tahoori
Keyword(s):
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