High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science
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Published By Springer Berlin Heidelberg

9783540775591, 9783540775607

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Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77560-7_11 ◽

2008 ◽

pp. 147-160 ◽

Cited By ~ 8

Author(s):

Todd T. Hahn ◽

Eric Stotzer ◽

Dineel Sule ◽

Mike Asal

Keyword(s):

Variable Length ◽

Code Size ◽

Vliw Processor

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rMPI: Message Passing on Multicore Processors with On-Chip Interconnect

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77560-7_3 ◽

2008 ◽

pp. 22-37 ◽

Cited By ~ 10

Author(s):

James Psota ◽

Anant Agarwal

Keyword(s):

Message Passing ◽

Multicore Processors ◽

On Chip

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MLP-Aware Dynamic Cache Partitioning

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77560-7_23 ◽

2008 ◽

pp. 337-352 ◽

Cited By ~ 12

Author(s):

Miquel Moreto ◽

Francisco J. Cazorla ◽

Alex Ramirez ◽

Mateo Valero

Keyword(s):

Cache Partitioning ◽

Dynamic Cache Partitioning

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Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77560-7_4 ◽

2008 ◽

pp. 38-52 ◽

Cited By ~ 10

Author(s):

Filip Blagojevic ◽

Xizhou Feng ◽

Kirk W. Cameron ◽

Dimitrios S. Nikolopoulos

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Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77560-7_22 ◽

2008 ◽

pp. 320-334 ◽

Cited By ~ 1

Author(s):

Frederik Vandeputte ◽

Lieven Eeckhout

Keyword(s):

Time Varying ◽

Program Behavior

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Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77560-7_24 ◽

2008 ◽

pp. 353-368 ◽

Cited By ~ 11

Author(s):

Subhradyuti Sarkar ◽

Dean M. Tullsen

Keyword(s):

Data Cache ◽

Multithreaded Architecture ◽

Cache Miss ◽

Compiler Techniques

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LPA: A First Approach to the Loop Processor Architecture

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77560-7_19 ◽

2008 ◽

pp. 273-287 ◽

Cited By ~ 1

Author(s):

Alejandro García ◽

Oliverio J. Santana ◽

Enrique Fernández ◽

Pedro Medina ◽

Mateo Valero

Keyword(s):

Processor Architecture

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Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77560-7_16 ◽

2008 ◽

pp. 224-239 ◽

Cited By ~ 1

Author(s):

Maziar Goudarzi ◽

Tohru Ishihara ◽

Hamid Noori

Keyword(s):

Process Variation ◽

Leakage Reduction

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Fast Bounds Checking Using Debug Register

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77560-7_8 ◽

2008 ◽

pp. 99-113 ◽

Cited By ~ 1

Author(s):

Tzi-cker Chiueh

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Drug Design Issues on the Cell BE

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science ◽

10.1007/978-3-540-77560-7_13 ◽

2008 ◽

pp. 176-190 ◽

Cited By ~ 5

Author(s):

Harald Servat ◽

Cecilia González-Alvarez ◽

Xavier Aguilar ◽

Daniel Cabrera-Benitez ◽

Daniel Jiménez-González

Keyword(s):

Drug Design ◽

Design Issues

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High Performance Embedded Architectures and Compilers - Lecture Notes in Computer ScienceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer Berlin Heidelberg

Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions

rMPI: Message Passing on Multicore Processors with On-Chip Interconnect

MLP-Aware Dynamic Cache Partitioning

Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE

Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior

Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture

LPA: A First Approach to the Loop Processor Architecture

Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation

Fast Bounds Checking Using Debug Register

Drug Design Issues on the Cell BE

High Performance Embedded Architectures and Compilers - Lecture Notes in Computer Science
Latest Publications