Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture

2012 ◽  
Vol 26 (1) ◽  
pp. 134-151
Author(s):  
Cheng-Yu Lee ◽  
Min-Chin Hung ◽  
Rong-Guey Chang
2007 ◽  
Vol 17 (2) ◽  
pp. 470-473 ◽  
Author(s):  
Igor I. Soloviev ◽  
M. Raihan Rafique ◽  
Henrik Engseth ◽  
Anna Kidiyarova-Shevchenko

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