A Lightweight AES Coprocessor Based on RISC-V Custom Instructions

With the increasing popularity of the Internet of Things (IoT), the issue of its information security has drawn more and more attention. To overcome the resource constraint barrier for secure and reliable data transmission on the widely used IoT devices such as wireless sensor network (WSN) nodes, many researcher studies consider hardware acceleration of traditional cryptographic algorithms as one of the effective methods. Meanwhile, as one of the current research topics in the reduced instruction set computer (RISC), RISC-V provides a solid foundation for implementing domain-specific architecture (DSA). To this end, we propose an extended instruction scheme for the advanced encryption standard (AES) based on RISC-V custom instructions and present a coprocessor designed on the open-source core Hummingbird E203. The AES coprocessor uses direct memory access channels to achieve parallel data access and processing, which provides flexibility in memory space allocation and improves the efficiency of cryptographic components. Applications with embedded AES custom instructions running on an experimental prototype of the field-programmable gate array (FPGA) platform demonstrated a 25.3% to 37.9% improvement in running time over previous similar works when processing no less than 80 bytes of data. In addition, the application-specific integrated circuit (ASIC) experiments show that in most cases, the coprocessor only consumes up to 20% more power than the necessary AES operations.

PERANCANGAN DAN PEMBUATAN MODUL ADC BERBASIS MIKROKONTROLER ATMEGA8535

Mikrokontroler AVR (Alf and Vegard RICS/ Reduced Instruction Set Computer) telah memiliki ADC 8 bit/ 10 bit internal dengan waktu konversi 65-260 µS sehingga lebih murah biayanya untuk merealisasi sistem mikrokontroler yang menggunakan ADC serta lebih praktis pengaplikasiannya. Modul ini penting dibuat untuk nantinya menjadi modul praktikum penggunaan ADC mikrokontroler AVR ATMEga8535 sebagai ADC 8 bit dan 10 bit. Pembuatan modul ini akan dapat memberikan pemahaman pada mahasiswa tentang bagaimana cara memanfaatkan kemampuan fungsi ADC pada mikrokontroler Atmega8535. Berdasarkan data yang didapat maka tingkat keakuratan data pada penggunaan ADC 10 bit lebih baik dengan beda selisih rata-rata 0,0018 sedangkan ADC 8 bit selisih rata-ratanya 0,0524. Dengan melakukan percobaan seperti pada modul yang dibuat maka mahasiswa diharapkan akan lebih memahami pengertian resolusi yang lebih baik pada penggunaan ADC 10 bit bila dibandingkan dengan ADC 8 bit. Dengan menampilkan di monitor sehingga penggunaannya lebih mudah maka diharapkan nantinya akan dapat memberikan pemahaman pada mahasiswa tentang bagaimana cara memanfaatkan kemampuan fungsi ADC pada mikrokontroler Atmega8535.

Matrix Manipulator

In computation involving matrices it is frequently necessary to interchange or rearrange rows or columns of a matrix. If the work is being done longhand or with a desk calculator, it is desirable to be able to perform the rearrangement without having to erase or rewrite numbers. In mathematics, matrix addition or subtraction, multiplication or the matrix product or any other arithmetic operation is a binary operation that produces a matrix from two matrices. The matrix manipulator was devised for the use in the Bureau’s statistical Engineering Laboratory for calculation with incidence matrices, i.e., matrices whose element are all 0’s or 1’s. So, through this project we will show how the matrix manipulation is taking place using MIPS programming language. MIPS is a reduced instruction set computer set architecture developed by MIPS Technologies. The early MIPS architecture was 32-bit with 64-bit versions added later. Also, the project is compiled to show Matrix addition of two different matrices, subtraction of two different matrices, multiplication, transpose, determinant, scaling of matrix.

Wireless Ultrasound Surgical System with Enhanced Power and Amplitude Performances

A wireless ultrasound surgical system (WUSS) with battery modules requires efficient power consumption with appropriate cutting effects during surgical operations. Effective cutting performances of the ultrasound transducer (UT) should be produced for ultrasound surgical knives for effective hemostasis performance and efficient dissection time. Therefore, we implemented a custom-made UT with piezoelectric material and re-poling process, which is applied to enhance the battery power consumption and output amplitude performances of the WUSS. After the re-poling process of the UT, the quality factor increased from 1231.1 to 2418 to minimize the unwanted heat generation. To support this UT, we also developed a custom-made generator with a transformer and developed 2nd harmonic termination circuit, control microcontroller with an advanced reduced instruction set computer machine (ARM) controller, and battery management system modules to produce effective WUSS performances. The generator with a matching circuit in the WUSS showed a peak-to-peak output voltage and current amplitude of 166 V and 1.12 A, respectively, at the resonant frequency. The performance with non-contact optical vibrators was also measured. In the experimental data, the developed WUSS reduced power consumption by 3.6% and increased the amplitude by 20% compared to those of the commercial WUSS. Therefore, the improved WUSS performances could be beneficial for hemostatic performance and dissection time during surgical operation because of the developed UT with a piezoelectric material and re-poling process.

An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method

The wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unacceptable analysis effort increase for multiple supply voltage nodes. Moreover, the foundry-provided timing libraries in the traditional STA (static timing analysis) approach are only available for the nominal supply voltage with limited voltage scaling, which cannot support timing verification for low voltages down to near- or sub-threshold voltages. In this paper, a learning-based approach for wide voltage design is proposed where feature engineering is performed to enhance the correlation among PVT corners based on a dilated CNN (convolutional neural network) model, and an ensemble model is utilized with two-layer stacking to improve timing prediction accuracy. The proposed method was verified with a commercial RISC (reduced instruction set computer) core under the supply voltage nodes ranging from 0.5 V to 0.9 V. Experimental results demonstrate that the prediction error is limited by 4.9% and 7.9%, respectively, within and across process corners for various working temperatures, which achieves up to 4.4× and 3.9× precision enhancement compared with related learning-based methods.

Modeling and Execution of Floating Point Parallel Processing Operation for RISC Processor

The development of processors with sundry suggestions have been made regarding a exactitude definition of RISC, but the prosaic concept is that such a computer has a small set of simple and prosaic instructions, instead of an outsized set of intricate and specialized instructions. This project proposes the planning of a high speed 64 bit RISC processor. The miens of this processor consume less power and it contrives on high speed. The processor comprises of sections namely Instruction Fetch section, Instruction Decode section, and Execution section. The ALU within the execution section comprises a double-precision floating-point multiplier designed during a corollary architecture thus improving the speed and veracity of the execution. All the sections are designed using Verilog coding. Monotonous instruction format, cognate prosaic-purpose registers, and pellucid addressing modes were the other miens. RISC exemplified as Reduced Instruction Set Computer. For designing high-performance processors, RISC is considered to be the footing. The RISC processor has a diminished number of Instructions, fixed instruction length, more prosaic-purpose register which are catalogued into the register file, load-store architecture and facilitate addressing modes which make diacritic instruction execute faster and achieve a net gain in performance. Thus the cardinal intent of this paper is to consummate the veridicality by devouring less power, area and with merest delay and it would be done by reinstating the floating-point ALU with single precision section by floating- point double precision section. Video processing, telecommunications and image processing were the high end applications used by architecture

An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors

Pipelines, in Reduced Instruction Set Computer (RISC) microprocessors, are expected to provide increased throughputs in most cases. However, there are a few instructions, and therefore entire assembly language codes, that execute faster and hazard-free without pipelines. It is usual for the compilers to generate codes from high level description that are more suitable for the underlying hardware to maintain symmetry with respect to performance; this, however, is not always guaranteed. Therefore, instead of trying to optimize the description to suit the processor design, we try to determine the more suitable processor variant for the given code during compile time, and dynamically reconfigure the system accordingly. In doing so, however, we first need to classify each code according to its suitability to a different processor variant. The latter, in turn, gives us confidence in performance symmetry against various types of codes—this is the primary contribution of the proposed work. We first develop mathematical performance models of three conventional microprocessor designs, and propose a symmetry-improving nonlinear optimization method to achieve code-to-design mapping. Our analysis is based on four different architectures and 324,000 different assembly language codes, each with between 10 and 1000 instructions with different percentages of commonly seen instruction types. Our results suggest that in the sub-micron era, where execution time of each instruction is merely in a few nanoseconds, codes accumulating as low as 5% (or above) hazard causing instructions execute more swiftly on processors without pipelines.