We address the prblem of time-stationary control synthesis for pipelined data paths.
Control synthesis system accepts scheduled control data flow graph with conditional
branches which are produced by high level synthesis tools such as Sehwa [1] as input
specification and generates a FSM controller. First a scheduled control/data flow graph
is analyzed and the various states are identified. Overlapped states are grouped together
to produce L groups where L is the pipeline latency. Next, state transitions are identified
and a state table is generated. Finally, a highly optimized FSM controller is
implemented by performing horizontal partitioning and the corresponding stae
encoding so as to minimize the total controller area. We compared our approach to
published work on FSM generation and optimization and the results indicate that our
method results in large savings in total controller area.