A New Arithmetic Unit in GF(2M) for Reconfigurable Hardware Implementation

Author(s):  
Chang Hoon Kim ◽  
Chun Pyo Hong ◽  
Soonhak Kwon ◽  
Yun Ki Kwon
1981 ◽  
Vol 10 (134) ◽  
Author(s):  
David W. Matula ◽  
Peter Kornerup

Based on the classical Euclidian Algorithm, we develop the foundations of an arithmetic unit performing Add, Subtract, Multiply and Divide on rational operands. The unit uses one unified algorithm for all operations, including rounding. A binary implementation, based on techniques known from the SRT division, is described. Finally, a hardware implementation using ripple-free, carry-save addition is analyzed, and adapted to a floating-slash representation of the rational operands.


Author(s):  
E. de Lucas ◽  
M. J. Miguel ◽  
D. Mozos ◽  
L. Vázquez

Abstract. Digital applications that must be on-board of space missions must accomplish a very restrictive set of requirements. These include energy efficiency, small volume and weight, robustness and high performance. Moreover these circuits can not be repaired in case of error, so they must be reliable or provide some way to recover from errors. These features make reconfigurable hardware (FPGAs, Field Programmable Gate Arrays) a very suitable technology to be used in space missions. This paper presents a Martian dust devil detector implemented on a FPGA. The results show that a hardware implementation of the algorithm present very good numbers in terms of performance compared with the software version. Moreover, as the amount of time needed to perform all the computations on the reconfigurable hardware is small, this hardware can be used more of the time to realize other applications.


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