Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools
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Published By IEEE Comput. Soc

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Enhanced configurable parallel memory architecture

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools ◽

10.1109/dsd.2002.1115348 ◽

2003 ◽

Author(s):

J. Vanne ◽

E. Aho ◽

K. Kuusilinna ◽

T. Hamalainen

Keyword(s):

Memory Architecture ◽

Parallel Memory

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Efficient verification of scheduling, allocation and binding in high-level synthesis

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools ◽

10.1109/dsd.2002.1115383 ◽

2003 ◽

Cited By ~ 1

Author(s):

J.M. Mendias ◽

R. Hermida ◽

M.C. Molina ◽

O. Penalba

Keyword(s):

High Level Synthesis ◽

High Level ◽

Efficient Verification

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Implementation of a streaming execution unit

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools ◽

10.1109/dsd.2002.1115364 ◽

2003 ◽

Author(s):

D. Cheresiz ◽

B. Juurlink ◽

S. Vassiliadis ◽

H.A.G. Wijshoff

Keyword(s):

Execution Unit

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Configurable memory organisation for communication applications

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools ◽

10.1109/dsd.2002.1115355 ◽

2003 ◽

Author(s):

J.-P. Soininen ◽

A. Pelkonen ◽

J. Roivainen

Keyword(s):

Memory Organisation

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An asynchronous victim cache

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools ◽

10.1109/dsd.2002.1115345 ◽

2003 ◽

Cited By ~ 1

Author(s):

D. Hormdee ◽

J.D. Garside ◽

S.B. Furber

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Improving mW/MHz ratio in FPGAs pipelined designs

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools ◽

10.1109/dsd.2002.1115379 ◽

2003 ◽

Author(s):

O. Cadenas ◽

G. Megson

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A flexible architecture for H.263 video coding

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools ◽

10.1109/dsd.2002.1115353 ◽

2003 ◽

Cited By ~ 1

Author(s):

M.J. Garrido ◽

C. Sanz ◽

M. Jimenez ◽

J.M. Meneses

Keyword(s):

Video Coding ◽

Flexible Architecture

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Reconfigurable hardware implementation of Montgomery modular multiplication and parallel binary exponentiation

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools ◽

10.1109/dsd.2002.1115373 ◽

2003 ◽

Cited By ~ 11

Author(s):

N. Nedjah ◽

L. de Macedo Mourelle

Keyword(s):

Hardware Implementation ◽

Reconfigurable Hardware ◽

Modular Multiplication ◽

Montgomery Modular Multiplication

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Integrating a computational model and a run time system for image processing on a UAV

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools ◽

10.1109/dsd.2002.1115357 ◽

2003 ◽

Author(s):

P. Andersson ◽

K. Kuchcinski ◽

K. Nordberg ◽

P. Doherty

Keyword(s):

Image Processing ◽

Computational Model ◽

Time System ◽

Run Time

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Constant coefficient convolution implemented in FPGAs

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools ◽

10.1109/dsd.2002.1115381 ◽

2003 ◽

Author(s):

E. Jamro ◽

K. Wiatr

Keyword(s):

Constant Coefficient

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Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and ToolsLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Enhanced configurable parallel memory architecture

Efficient verification of scheduling, allocation and binding in high-level synthesis

Implementation of a streaming execution unit

Configurable memory organisation for communication applications

An asynchronous victim cache

Improving mW/MHz ratio in FPGAs pipelined designs

A flexible architecture for H.263 video coding

Reconfigurable hardware implementation of Montgomery modular multiplication and parallel binary exponentiation

Integrating a computational model and a run time system for image processing on a UAV

Constant coefficient convolution implemented in FPGAs

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools
Latest Publications