High Performance Reconfigurable Elliptic Curve Cipher Processor Implementation

Elliptic Curve Encryption (ECC) has been widely used in the field of digital signatures in communication security. ECC standards and the diversification of application scenarios put forward higher requirements for the flexibility of ECC processors. Therefore, it is necessary to design a flexible and reconfigurable processor to adapt to changing standards. The cryptographic processor chip designed in this paper supports the choice of prime and binary fields, supports the maximum key length of 576 bits, uses microcode programming to achieve reconfigurable function, and significantly improves the flexibility of the dedicated cryptographic processor. At the same time, the speed of modular multiplication and modular division can be greatly improved under the condition of keeping the low level of hardware resources through a carefully designed modular unit of operation. After using FPGA for hardware implementation, it is configured into a 256-bit key length. The highest clock frequency of this design can reach 55.7MHz, occupying 12425LUTS. Compared with a similar design, the performance is also greatly improved. After MALU module optimization design, modular multiplication module division also has significant advantages in computing time consumption.

ANALYSIS AND SOFTWARE IMPLEMENTATION OF MODULAR MULTIPLICATION-BASED BLOCK CIPHER

This article highlights the ever-increasing need and importance of information protection and data safety in modern reality, presents the possibilities of encrypting data using the tools of cryptography, particularly concentrating on the Modular Multiplication-based Block Cipher. Review of available sources indicated that there are no publically accessible software implementations of the algorithm available at the moment of writing this article. To achieve a goal of creating such an implementation, information has been compiled for creating a comprehensible and adequate mathematical description of the algorithm. Presented the information security system, an application in C # to encrypt files of any extension using the block encryption algorithm MMB

The Improvement of Elliptic Curve Factorization Method to Recover RSA’s Prime Factors

Elliptic Curve Factorization Method (ECM) is the general-purpose factoring method used in the digital computer era. It is based on the medium length of the modulus; ECM is an efficient algorithm when the length of modulus is between 40 and 50 digits. In fact, the main costs for each iteration are modular inverse, modular multiplication, modular square and greatest common divisor. However, when compared to modular multiplication and modular square, the costs of modular inverse and greatest common divisor are very high. The aim of this paper is to improve ECM in order to reduce the costs to compute both of modular inverse and greatest common divisor. The proposed method is called Fast Elliptic Curve Factorization Method (F-ECM). For every two adjacent points on the curve, only one modular inverse and one greatest common divisor will be computed. That means it implies that the costs in both of them can be split in half. Furthermore, the length of modulus in the experiment spans from 30 to 65 bits. The experimental results show that F-ECM can finish the task faster than ECM for all cases of the modulus. Furthermore, the computation time is reduced by 30 to 38 percent.

A Hardware-Efficient Elliptic Curve Cryptographic Architecture over GF (p)

This paper proposes a hardware-efficient elliptic curve cryptography (ECC) architecture over GF(p), which uses adders to achieve scalar multiplication (SM) through hardware-reuse method. In terms of algorithm, the improvement of the interleaved modular multiplication (IMM) algorithm and the binary modular inverse (BMI) algorithm needs two adders. In addition to the adder, the data register is another optimize target. The design compiler is synthesized on 0.13 µm CMOS ASIC platform. The time range of performing scalar multiplication over 160, 192, 224, and 256 field orders under 150 MHz frequency is 1.99–3.17 ms. Moreover, the gate area required for different field orders in this design is in the range of 35.65k–59.14k, with 50%–91% hardware resource less than other processors.