Timing Analysis for Sequential Circuits

Timing ◽  
2006 ◽  
pp. 133-150
Keyword(s):  
Timing Analysis ◽  
Sequential Circuits

Timing Analysis of Sequential Circuits

1999 ◽  
pp. 7-31
Author(s):  
Naresh Maheshwari ◽  
Sachin S. Sapatnekar
Keyword(s):  
Timing Analysis ◽  
Sequential Circuits

Timing Analysis and Optimization of Sequential Circuits

1999 ◽  
Author(s):  
Naresh Maheshwari ◽  
Sachin S. Sapatnekar
Keyword(s):  
Timing Analysis ◽  
Sequential Circuits

Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration

2016 ◽  
Vol E99.A (12) ◽  
pp. 2320-2327
Author(s):  
Cheng-Yu HAN ◽  
Yu-Ching LI ◽  
Hao-Tien KAN ◽  
James Chien-Mo LI
Keyword(s):  
Power Supply ◽  
Test Pattern ◽  
Timing Analysis ◽  
Power Supply Noise ◽  
Supply Noise

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level

2010 ◽  
Vol 52 (4) ◽  
Author(s):  
Dominik Lorenz ◽  
Georg Georgakos ◽  
Ulf Schlichtmann
Keyword(s):  
Timing Analysis ◽  
Combinatorial Circuits

Timing analysis of worst case with direct NM of OSEK NM

2008 ◽  
Author(s):  
Chang-Wan Son ◽  
Jin-Ho Kim ◽  
Tae-Yoon Moon ◽  
Key-Ho Kwon ◽  
Sung-Ho Hwang ◽  
...  
Keyword(s):  
Timing Analysis ◽  
Worst Case
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