Maximizing ATPG Diagnosis Resolution on Unique Single Failing Devices

Unique single failing device is common for customer returns and reliability failures. When the initial and iterative Automatic Test Pattern Generator (ATPG) could not provide a sufficient diagnostic resolution, it can become quite challenging for the analyst to determine the failure mechanism in an efficient and effective way. Fault isolation could be performed in combination with the diagnosis results but there are cases with mismatch between the results (location, fault type, suspect nets). When the diagnostic resolution is low, the probability for such mismatches are high. This paper proposes an approach to increase the diagnostic resolution by utilizing a high-resolution targeted pattern (HRT) and single shot logic (SSL) patterns. Two cases will be discussed in the paper to highlight this approach and show in detail how it was utilized on actual failing units.

Achieving Submicrometer Spatial Resolution for Neutron Imaging With Nuclear Emulsion

Neutron imaging is a non-destructive inspection technique with a wide range of potential applications. One of the key technical interests concerning neutron imaging is to achieve micrometer-scale spatial resolution. However, developing a neutron detector with a high spatial resolution is a challenging task. Recent efforts are focused on achieving this milestone or even submicrometer spatial resolution. Herein, we introduce our technique for neutron imaging using a fine-grained nuclear emulsion and evaluate the spatial resolution. We used the fine-grained nuclear emulsion with a gadolinium-based Siemens star test pattern and a grating with a periodic structure of 9 μm. The deduced value of the spatial resolution is less than 1 μm using the developed technique. To the best of our knowledge, the submicrometer spatial resolution that we achieved using our method is the best among all reported neutron imaging devices.

Design of a 1.9 GHz low-power LFSR Circuit using the Reed-Solomon Algorithm for Pseudo-Random Test Pattern Generation

A linear feedback shift register (LFSR) has been frequently used in the Built-in Self-Test (BIST) designs for the pseudo-random test pattern generation. The higher volume of the test patterns and the lower test power consumption are the key features in the large complex designs. The motivation of this study is to generate efficient pseudo-random test patterns by the proposed LFSR and to be applied in the BIST designs. For the BIST designs, the proposed LFSR satisfied with the main strategies such as re-seeding and lesser test power consumption. However, the reseeding approach was utilized by the maximum-length pseudo-random test patterns. The objective of this paper is to propose a new LFSR circuit based on the proposed Reed-Solomon (RS) algorithm. The RS algorithm is created by considering the factors of the maximum length test patterns with a minimum distance over the time t. Also, it has been achieved an effective generation of test patterns over a stage of complexity order O (m log2 m), where m denotes the total number of message bits. We analysed our RS LFSR mathematically using the feedback polynomial function to decrease the area overhead occupied in the designs. The simulation works of the proposed RS LFSR bit-wise stages are simulated using the TSMC 130 nm on the Mentor Graphics IC design platform. Experimental results showed that the proposed LFSR achieved the effective pseudo-random test patterns with a lower test power consumption of 25.13 µW and 49.9 µs. In addition, proposed LFSR along with existing authors’ LFSR are applied in the BIST design to examine their power consumption. Ultimately, overall simulations operated with the highest operating frequency environment as 1.9 GHz.