Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units

Lecture Notes in Computer Science - Correct Hardware Design and Verification Methods ◽

10.1007/11560548_10 ◽

2005 ◽

pp. 97-113 ◽

Author(s):

Miroslav N. Velev

Keyword(s):

Formal Verification ◽

Functional Units ◽

Pipelined Processors

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Exploiting Abstraction for Efficient Formal Verification of DSPs with Arrays of Reconfigurable Functional Units

Formal Methods and Software Engineering - Lecture Notes in Computer Science ◽

10.1007/978-3-642-24559-6_22 ◽

2011 ◽

pp. 307-322 ◽

Author(s):

Miroslav N. Velev ◽

Ping Gao

Keyword(s):

Formal Verification ◽

Functional Units

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A method for debugging of pipelined processors in formal verification by Correspondence Checking

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419811 ◽

2010 ◽

Author(s):

Miroslav N. Velev ◽

Ping Gao

Keyword(s):

Formal Verification ◽

Pipelined Processors

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Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction

Proceedings 37th Design Automation Conference ◽

10.1145/337292.337331 ◽

2000 ◽

Author(s):

Miroslav N. Velev ◽

Randal E. Bryant

Keyword(s):

Formal Verification ◽

Branch Prediction ◽

Functional Units

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Formal verification of pipelined processors with precise exceptions

Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. ◽

10.1109/memcod.2004.1459832 ◽

2005 ◽

Author(s):

K. Kalyanasundaram ◽

R.K. Shyammundar

Keyword(s):

Formal Verification ◽

Pipelined Processors

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Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction

7th International Symposium on Quality Electronic Design (ISQED'06) ◽

10.1109/isqed.2006.142 ◽

2006 ◽

Author(s):

M.N. Velev

Keyword(s):

Formal Verification ◽

Value Prediction ◽

Pipelined Processors

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Formal verification of pipelined processors

Tools and Algorithms for the Construction and Analysis of Systems - Lecture Notes in Computer Science ◽

10.1007/bfb0054160 ◽

1998 ◽

pp. 1-4

Author(s):

Randal E. Bryant

Keyword(s):

Formal Verification ◽

Pipelined Processors

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Efficient formal verification of pipelined processors with instruction queues

Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04 ◽

10.1145/988952.988975 ◽

2004 ◽

Author(s):

Miroslav N. Velev

Keyword(s):

Formal Verification ◽

Pipelined Processors

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Formal verification of pipelined processors with load-value prediction

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) ◽

10.1109/hldvt.2004.1431231 ◽

2004 ◽

Author(s):

M.N. Velev

Keyword(s):

Formal Verification ◽

Value Prediction ◽

Pipelined Processors

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Formal Verification of Analysis Approach for Enterprise Information Systems Architecture Using Hypergraph Representation Based on Finite State Machines for Supporting Business Process Requirements

Journal of Applied Business and Economics ◽

10.33423/jabe.v22i9.3686 ◽

2020 ◽

Vol 22 (9) ◽

Keyword(s):

Information Systems ◽

Formal Verification ◽

Business Process ◽

Analysis Approach ◽

State Machines ◽

Enterprise Information ◽

Systems Architecture ◽

Enterprise Information Systems ◽

Finite State ◽

Information Systems Architecture

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Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors

IEICE Transactions on Electronics ◽

10.1587/transele.e96.c.463 ◽

2013 ◽

Vol E96.C (4) ◽

pp. 463-472

Author(s):

Kazuhito ITO ◽

Takuya NUMATA

Keyword(s):

Energy Dissipation ◽

General Purpose ◽

General Purpose Processors ◽

Functional Units

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