State/Event Software Verification for Branching-Time Specifications

2005 ◽  
pp. 53-69 ◽  
Author(s):  
Sagar Chaki ◽  
Edmund Clarke ◽  
Orna Grumberg ◽  
Joël Ouaknine ◽  
Natasha Sharygina ◽  
...  
Keyword(s):  
Software Verification ◽  
Branching Time

Synthesizing Conjunctive & Disjunctive Linear Invariants by K-means++ and SVM

2020 ◽  
Vol 17 (6) ◽  
pp. 847-856
Author(s):  
Shengbing Ren ◽  
Xiang Zhang
Keyword(s):  
Software Verification ◽  
State Of The Art ◽  
Positive Sample ◽  
Machine Learning Algorithms ◽  
Support Vector ◽  
Hoare Logic ◽  
Excellent Performance ◽  
Automated Software ◽  
Inductive Invariants ◽  
Linear Invariants

The problem of synthesizing adequate inductive invariants lies at the heart of automated software verification. The state-of-the-art machine learning algorithms for synthesizing invariants have gradually shown its excellent performance. However, synthesizing disjunctive invariants is a difficult task. In this paper, we propose a method k++ Support Vector Machine (SVM) integrating k-means++ and SVM to synthesize conjunctive and disjunctive invariants. At first, given a program, we start with executing the program to collect program states. Next, k++SVM adopts k-means++ to cluster the positive samples and then applies SVM to distinguish each positive sample cluster from all negative samples to synthesize the candidate invariants. Finally, a set of theories founded on Hoare logic are adopted to check whether the candidate invariants are true invariants. If the candidate invariants fail the check, we should sample more states and repeat our algorithm. The experimental results show that k++SVM is compatible with the algorithms for Intersection Of Half-space (IOH) and more efficient than the tool of Interproc. Furthermore, it is shown that our method can synthesize conjunctive and disjunctive invariants automatically

scholarly journals SAT modulo discrete event simulation applied to railway design capacity analysis

2021 ◽  
Author(s):  
Bjørnar Luteberget ◽  
Koen Claessen ◽  
Christian Johansen ◽  
Martin Steffen
Keyword(s):  
Discrete Event Simulation ◽  
Construction Projects ◽  
Software Verification ◽  
Ad Hoc ◽  
Discrete Event ◽  
Capacity Analysis ◽  
Railway Network ◽  
Event Simulation ◽  
Design Engineers ◽  
Railway Capacity

AbstractThis paper proposes a new method of combining SAT with discrete event simulation. This new integration proved useful for designing a solver for capacity analysis in early phase railway construction design. Railway capacity is complex to define and analyze, and existing tools and methods used in practice require comprehensive models of the railway network and its timetables. Design engineers working within the limited scope of construction projects report that only ad-hoc, experience-based methods of capacity analysis are available to them. Designs often have subtle capacity pitfalls which are discovered too late, only when network-wide timetables are made—there is a mismatch between the scope of construction projects and the scope of capacity analysis, as currently practiced. We suggest a language for capacity specifications suited for construction projects, expressing properties such as running time, train frequency, overtaking and crossing. Such specifications can be used as contracts in the interface between construction projects and network-wide capacity analysis. We show how these properties can be verified fully automatically by building a special-purpose solver which splits the problem into two: an abstracted SAT-based dispatch planning, and a continuous-domain dynamics with timing constraints evaluated using discrete event simulation. The two components communicate in a CEGAR loop (counterexample-guided abstraction refinement). This architecture is beneficial because it clearly distinguishes the combinatorial choices on the one hand from continuous calculations on the other, so that the simulation can be extended by relevant details as needed. We describe how loops in the infrastructure can be handled to eliminate repeating dispatch plans, and use case studies based on data from existing infrastructure and ongoing construction projects to show that our method is fast enough at relevant scales to provide agile verification in a design setting. Similar SAT modulo discrete event simulation combinations could also be useful elsewhere where one or both of these methods are already applicable such as in bioinformatics or hardware/software verification.

scholarly journals Software Verification and Validation of Safe Autonomous Cars: A Systematic Literature Review

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 4797-4819
Author(s):  
Nijat Rajabli ◽  
Francesco Flammini ◽  
Roberto Nardone ◽  
Valeria Vittorini
Keyword(s):  
Literature Review ◽  
Systematic Literature Review ◽  
Software Verification ◽  
Verification And Validation ◽  
Autonomous Cars ◽  
Software Verification And Validation

scholarly journals An obstacle to sub-AdS holography for SYK-like models

2021 ◽  
Vol 2021 (3) ◽  
Author(s):  
Pengfei Zhang ◽  
Yingfei Gu ◽  
Alexei Kitaev
Keyword(s):  
Lyapunov Exponent ◽  
Weak Coupling ◽  
Kinetic Coefficient ◽  
Weak Coupling Limit ◽  
Branching Time ◽  
Quasiparticle Lifetime

Abstract We argue that “stringy” effects in a putative gravity-dual picture for SYK-like models are related to the branching time, a kinetic coefficient defined in terms of the retarded kernel. A bound on the branching time is established assuming that the leading diagrams are ladders with thin rungs. Thus, such models are unlikely candidates for sub-AdS holography. In the weak coupling limit, we derive a relation between the branching time, the Lyapunov exponent, and the quasiparticle lifetime using two different approximations.

scholarly journals Constructing weak simulations from linear implications for processes with private names

2019 ◽  
Vol 29 (8) ◽  
pp. 1275-1308 ◽  
Author(s):  
Ross Horne ◽  
Alwen Tiu
Keyword(s):  
Expressive Power ◽  
Dual Pair ◽  
Proof System ◽  
Branching Time ◽  
First Order ◽  
Order Extension

AbstractThis paper clarifies that linear implication defines a branching-time preorder, preserved in all contexts, when used to compare embeddings of process in non-commutative logic. The logic considered is a first-order extension of the proof system BV featuring a de Morgan dual pair of nominal quantifiers, called BV1. An embedding of π-calculus processes as formulae in BV1 is defined, and the soundness of linear implication in BV1 with respect to a notion of weak simulation in the π -calculus is established. A novel contribution of this work is that we generalise the notion of a ‘left proof’ to a class of formulae sufficiently large to compare embeddings of processes, from which simulating execution steps are extracted. We illustrate the expressive power of BV1 by demonstrating that results extend to the internal π -calculus, where privacy of inputs is guaranteed. We also remark that linear implication is strictly finer than any interleaving preorder.

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