Scheduling Fault-Tolerant Programs on Multiple Processors to Maximize Schedule Reliability

The paper proposes a new reliable fault-tolerant scheduling algorithm for real-time embedded systems. The proposed algorithm is based on static scheduling that allows to include the dependencies and the execution cost of tasks and data dependencies in its scheduling decisions. Our scheduling algorithm is dedicated to multi-bus heterogeneous architectures with multiple processors linked by several shared buses. This scheduling algorithm is considering only one bus fault caused by hardware faults and compensated by software redundancy solutions. The proposed algorithm is based on both active and passive backup copies to minimize the scheduling length of data on buses. In the experiments, the proposed methods are evaluated in terms of data scheduling length for a set of DSP benchmarks. The experimental results show the effectiveness of our technique.

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Fault-tolerant and flexible interconnection of multiple processors

Information Processing Letters ◽

10.1016/0020-0190(88)90201-3 ◽

1988 ◽

Vol 28 (5) ◽

pp. 259-268

Author(s):

P.K. Das ◽

D.Q.M. Fay

Keyword(s):

Fault Tolerant ◽

Multiple Processors

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Evolution-based scheduling of fault-tolerant programs on multiple processors

Lecture Notes in Computer Science - Parallel and Distributed Processing ◽

10.1007/bfb0097902 ◽

1999 ◽

pp. 210-219 ◽

Cited By ~ 5

Author(s):

Piotr Jedrzejowicz ◽

Ireneusz Czarnowski ◽

Henryk Szreder ◽

Aleksander Skakowski

Keyword(s):

Fault Tolerant ◽

Multiple Processors

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Design of Fault Tolerant Shuffle Exchange Gamma Interconnection Network Layouts

Journal of Interconnection Networks ◽

10.1142/s0219265917500050 ◽

2017 ◽

Vol 17 (02) ◽

pp. 1750005 ◽

Cited By ~ 5

Author(s):

GAURAV KHANNA ◽

RAJESH MISHRA ◽

S. K. CHATURVEDI

Keyword(s):

Interconnection Networks ◽

Fault Tolerant ◽

Interconnection Network ◽

Cost Effective ◽

Disjoint Paths ◽

Multiple Processors ◽

Memory Modules ◽

Telephone Industry ◽

Exchange Network ◽

Shuffle Exchange Network

Advancement in technology has resulted in increased computing power with the use of multiple processors within a system. These multiple processors need to communicate with each other and with memory modules. Multistage Interconnection Networks (MINs) provide a communication medium in such multi-processor systems by interconnecting a number of processors and memory modules. Besides, MINs also provide a cost effective substitute to costly crossbars in parallel computers and switching systems in telephone industry. This paper introduces two new fault-tolerant MINs named as Shuffle Exchange Gamma Interconnection Networks (SEGIN-1 and SEGIN-2). SEGIN-1 and SEGIN-2 can be obtained by altering Shuffle Exchange Network with one extra stage (SEN+) and provide two disjoint paths similar to it. Performance of SEGIN-1 and SEGIN-2 has been evaluated in terms of alternative paths, disjoint paths, reliability and hardware cost, and is compared with some very famous MINs like Shuffle Exchange Network (SEN), Shuffle Exchange Network with one extra stage (SEN+), Shuffle Exchange Network with two extra stage (SEN+2), Extra Stage Cube (ESC) and Gamma Interconnection Network (GIN). Results suggest that SEGINs surpass all the compared networks; hence, the proposed designs seem to be suitable for implementing practical interconnection networks.

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SEGIN-Minus: A New Approach to Design Reliable and Fault-Tolerant MIN

Recent Advances in Computer Science and Communications ◽

10.2174/2213275912666181207153651 ◽

2020 ◽

Vol 13 (3) ◽

pp. 370-380

Author(s):

Shilpa Gupta ◽

Gobind Lal Pahuja

Keyword(s):

Fault Tolerance ◽

Interconnection Networks ◽

Fault Tolerant ◽

Interconnection Network ◽

Network Reliability ◽

Low Cost ◽

Destination Node ◽

Node Pair ◽

Output Terminal ◽

Multiple Processors

Background: VLSI technology advancements have resulted the requirements of high computational power, which can be achieved by implementing multiple processors in parallel. These multiple processors have to communicate with their memory modules by using Interconnection Networks (IN). Multistage Interconnection Networks (MIN) are used as IN, as they provide efficient computing with low cost. Objective: the objective of the study is to introduce new reliable MIN named as a (Shuffle Exchange Gamma Interconnection Network Minus) SEGIN-Minus, which provide reliability and faulttolerance with less number of stages. Methods: MUX at input terminal and DEMUX at output terminal of SEGIN has been employed with reduction in one intermidiate stage. Fault tolerance has been introduced in the form of disjoint paths formed between each source-destnation node pair. Hence reliability has been improved. Results: Terminal, Broadcast and Network Reliability has been evaluated by using Reliability Block Diagrams for each source-destination node pair. The results have been shown, which depicts the hiher reliability values for newly proposed network. The cost analysis shows that new SEGINMinus is a cheaper network than SEGIN. Conclusion: SEGIN-Minus has better reliability and Fault-tolerance than priviously proposed SEGIN.

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