SEGIN-Minus: A New Approach to Design Reliable and Fault-Tolerant MIN

2020 ◽  
Vol 13 (3) ◽  
pp. 370-380
Author(s):  
Shilpa Gupta ◽  
Gobind Lal Pahuja
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Network Reliability ◽  
Low Cost ◽  
Destination Node ◽  
Node Pair ◽  
Output Terminal ◽  
Multiple Processors

Background: VLSI technology advancements have resulted the requirements of high computational power, which can be achieved by implementing multiple processors in parallel. These multiple processors have to communicate with their memory modules by using Interconnection Networks (IN). Multistage Interconnection Networks (MIN) are used as IN, as they provide efficient computing with low cost. Objective: the objective of the study is to introduce new reliable MIN named as a (Shuffle Exchange Gamma Interconnection Network Minus) SEGIN-Minus, which provide reliability and faulttolerance with less number of stages. Methods: MUX at input terminal and DEMUX at output terminal of SEGIN has been employed with reduction in one intermidiate stage. Fault tolerance has been introduced in the form of disjoint paths formed between each source-destnation node pair. Hence reliability has been improved. Results: Terminal, Broadcast and Network Reliability has been evaluated by using Reliability Block Diagrams for each source-destination node pair. The results have been shown, which depicts the hiher reliability values for newly proposed network. The cost analysis shows that new SEGINMinus is a cheaper network than SEGIN. Conclusion: SEGIN-Minus has better reliability and Fault-tolerance than priviously proposed SEGIN.

Modified Gamma Network: Design and Reliability Evaluation

2019 ◽  
Vol 13 ◽  
Author(s):  
Shilpa Gupta ◽  
Gobind Lal Pahuja
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Interconnection Network ◽  
Network Reliability ◽  
Destination Node ◽  
Input Output ◽  
Switching Element ◽  
Node Pair ◽  
Multiple Processors ◽  
Output Stages

Background: VLSI technology advancements have resulted the requirements of high computational power, which can be achieved by implementing multiple processors in parallel. These multiple processors have to communicate with their memory modules by using Interconnection Networks (IN). Multistage Interconnection networks (MIN) are used as IN, as they provide efficient computing with low cost. Objective: the objective of the study is to introduce new reliable Gamma MIN named as a Modified Gamma Interconnection Network (MGIN), which provide reliability and fault-tolerance with less number of stages of Switching element only. Method: Switching Element (SE) of bigger size i.e. 2×3/3×2 has been employed at input/output stages inspite of 1×3/3×1 sized SE at input/output stages with reduction in one intermidiate stage. Fault tolerance has been introduced in the form of disjoint paths formed between each source-destnation node pair. Hence reliability has been improved. Results: Terminal, Broadcast and Network Reliability has been evaluated by using Reliability Block Diagrams for each source-destination node pair. The results have been shown, which depicts the higher reliability values for newly proposed network. The cost analysis shows that new MGIN is a cheaper network than other Gamma variants. Conclusion: MGIN has better reliability and Fault-tolerance than priviously proposed Gamma MIN.

Designing a New Class of Fault Tolerant Multistage Interconnection Networks

2005 ◽  
Vol 06 (04) ◽  
pp. 361-382 ◽  
Author(s):  
K. V. Arya ◽  
R. K. Ghosh
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Multistage Interconnection Networks ◽  
Multistage Interconnection Network ◽  
New Class

This paper proposes a technique to modify a Multistage Interconnection Network (MIN) to augment it with fault tolerant capabilities. The augmented MIN is referred to as Enhanced MIN (E-MIN). The technique employed for construction of E-MIN is compared with the two known physical fault tolerance techniques, namely, extra staging and chaining. EMINs are found to be more generic than extra staged networks and less expensive than chained networks. The EMIN realizes all the permutations realizable by the original MIN. The routing strategies under faulty and fault free conditions are shown to be very simple in the case of E-MINs.

Fault-Tolerant Maximal Local-Connectivity on Cayley Graphs Generated by Transpositions

2019 ◽  
Vol 30 (08) ◽  
pp. 1301-1315 ◽  
Author(s):  
Liqiong Xu ◽  
Shuming Zhou ◽  
Weihua Yang
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Cayley Graphs ◽  
Disjoint Paths ◽  
Local Connectivity ◽  
Communication Links ◽  
Restricted Condition ◽  
Vertex Disjoint

An interconnection network is usually modeled as a graph, in which vertices and edges correspond to processors and communication links, respectively. Connectivity is an important metric for fault tolerance of interconnection networks. A graph [Formula: see text] is said to be maximally local-connected if each pair of vertices [Formula: see text] and [Formula: see text] are connected by [Formula: see text] vertex-disjoint paths. In this paper, we show that Cayley graphs generated by [Formula: see text]([Formula: see text]) transpositions are [Formula: see text]-fault-tolerant maximally local-connected and are also [Formula: see text]-fault-tolerant one-to-many maximally local-connected if their corresponding transposition generating graphs have a triangle, [Formula: see text]-fault-tolerant one-to-many maximally local-connected if their corresponding transposition generating graphs have no triangles. Furthermore, under the restricted condition that each vertex has at least two fault-free adjacent vertices, Cayley graphs generated by [Formula: see text]([Formula: see text]) transpositions are [Formula: see text]-fault-tolerant maximally local-connected if their corresponding transposition generating graphs have no triangles.

A novel design layout of three disjoint paths multistage interconnection network & its reliability analysis

2021 ◽  
Vol 17 (4) ◽  
pp. 390-403
Author(s):  
Vipin Sharma ◽  
Abdul Q. Ansari ◽  
Rajesh Mishra
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Interconnection Network ◽  
High Reliability ◽  
Block Diagram ◽  
Low Cost ◽  
Disjoint Paths ◽  
Content Type ◽  
Multistage Interconnection Network ◽  
Terminal Reliability

Purpose The purpose of this paper is to design a efficient layout of Multistage interconnection network which has cost effective solution with high reliability and fault-tolerence capability. For parallel computation, various multistage interconnection networks (MINs) have been discussed hitherto in the literature, however, these networks always required further improvement in reliability and fault-tolerance capability. The fault-tolerance capability of the network can be achieved by increasing the number of disjoint paths as a result the reliability of the interconnection networks is also improved. Design/methodology/approach This proposed design is a modification of gamma interconnection network (GIN) and three disjoint path gamma interconnection network (3-DGIN). It has a total seven number of paths for all tag values which is uniform out of these seven paths, three paths are disjoint paths which increase the fault tolerance capability by two faults. Due to the presence of more paths than the GIN and 3-DGIN, this proposed design is more reliable. Findings In this study, a new design layout of a MIN has been proposed which provides three disjoint paths and uniformity in terms of an equal number of paths for all source-destination (S-D) pairs. The new layout contains fewer nodes as compared to GIN and 3-DGIN. This design provides a symmetrical structure, low cost, better terminal reliability and provides an equal number of paths for all tag values (|S-D|) when compared with existing MINs of this class. Originality/value A new design layout of MINs has been purposed and its two terminal reliability is calculated with the help of the reliability block diagram technique.

Design of Fault Tolerant Shuffle Exchange Gamma Interconnection Network Layouts

2017 ◽  
Vol 17 (02) ◽  
pp. 1750005 ◽  
Author(s):  
GAURAV KHANNA ◽  
RAJESH MISHRA ◽  
S. K. CHATURVEDI
Keyword(s):  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Cost Effective ◽  
Disjoint Paths ◽  
Multiple Processors ◽  
Memory Modules ◽  
Telephone Industry ◽  
Exchange Network ◽  
Shuffle Exchange Network

Advancement in technology has resulted in increased computing power with the use of multiple processors within a system. These multiple processors need to communicate with each other and with memory modules. Multistage Interconnection Networks (MINs) provide a communication medium in such multi-processor systems by interconnecting a number of processors and memory modules. Besides, MINs also provide a cost effective substitute to costly crossbars in parallel computers and switching systems in telephone industry. This paper introduces two new fault-tolerant MINs named as Shuffle Exchange Gamma Interconnection Networks (SEGIN-1 and SEGIN-2). SEGIN-1 and SEGIN-2 can be obtained by altering Shuffle Exchange Network with one extra stage (SEN+) and provide two disjoint paths similar to it. Performance of SEGIN-1 and SEGIN-2 has been evaluated in terms of alternative paths, disjoint paths, reliability and hardware cost, and is compared with some very famous MINs like Shuffle Exchange Network (SEN), Shuffle Exchange Network with one extra stage (SEN+), Shuffle Exchange Network with two extra stage (SEN+2), Extra Stage Cube (ESC) and Gamma Interconnection Network (GIN). Results suggest that SEGINs surpass all the compared networks; hence, the proposed designs seem to be suitable for implementing practical interconnection networks.

Component Edge Connectivity of Hypercubes

2018 ◽  
Vol 29 (06) ◽  
pp. 995-1001 ◽  
Author(s):  
Shuli Zhao ◽  
Weihua Yang ◽  
Shurong Zhang ◽  
Liqiong Xu
Keyword(s):  
Fault Tolerance ◽  
Complete Graph ◽  
Interconnection Networks ◽  
Interconnection Network ◽  
Optimal Solutions ◽  
Edge Connectivity ◽  
Important Measure ◽  
Minimum Number ◽  
Text Component

Fault tolerance is an important issue in interconnection networks, and the traditional edge connectivity is an important measure to evaluate the robustness of an interconnection network. The component edge connectivity is a generalization of the traditional edge connectivity. The [Formula: see text]-component edge connectivity [Formula: see text] of a non-complete graph [Formula: see text] is the minimum number of edges whose deletion results in a graph with at least [Formula: see text] components. Let [Formula: see text] be an integer and [Formula: see text] be the decomposition of [Formula: see text] such that [Formula: see text] and [Formula: see text] for [Formula: see text]. In this note, we determine the [Formula: see text]-component edge connectivity of the hypercube [Formula: see text], [Formula: see text] for [Formula: see text]. Moreover, we classify the corresponding optimal solutions.

THE CUBE-OF-RINGS INTERCONNECTION NETWORK

1998 ◽  
Vol 09 (01) ◽  
pp. 25-37 ◽  
Author(s):  
THOMAS J. CORTINA ◽  
ZHIWEI XU
Keyword(s):  
Graph Theory ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Parallel Computers ◽  
Closed Form Expression ◽  
Form Expression ◽  
Graph Theoretic ◽  
Basic Graph

We present a family of interconnection networks named the Cube-Of-Rings (COR) networks along with their basic graph-theoretic properties. Aspects of group graph theory are used to show the COR networks are symmetric and optimally fault tolerant. We present a closed-form expression of the diameter and optimal one-to-one routing algorithm for any member of the COR family. We also discuss the suitability of the COR networks as the interconnection network of scalable parallel computers.

scholarly journals Topological Properties of Hierarchical Interconnection Networks: A Review and Comparison

2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Mostafa Abd-El-Barr ◽  
Turki F. Al-Somani
Keyword(s):  
Packing Density ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Parallel Applications ◽  
Topological Properties ◽  
Remote Communication ◽  
Chip Area ◽  
Network Diameter ◽  
Link Cost

Hierarchical interconnection networks (HINs) provide a framework for designing networks with reduced link cost by taking advantage of the locality of communication that exists in parallel applications. HINs employ multiple levels. Lower-level networks provide local communication while higher-level networks facilitate remote communication. HINs provide fault tolerance in the presence of some faulty nodes and/or links. Existing HINs can be broadly classified into two classes. those that use nodes and/or links replication and those that use standby interface nodes. The first class includes Hierarchical Cubic Networks, Hierarchical Completely Connected Networks, and Triple-based Hierarchical Interconnection Networks. The second HINs class includes Modular Fault-Tolerant Hypercube Networks and Hierarchical Fault-Tolerant Interconnection Network. This paper presents a review and comparison of the topological properties of both classes of HINs. The topological properties considered are network degree, diameter, cost and packing density. The outcome of this study show among all HINs two networks that is, the Root-Folded Heawood (RFH) and the Flooded Heawood (FloH), belonging to the first HIN class provide the best network cost, defined as the product of network diameter and degree. The study also shows that HFCube(n,n)provide the best packing density, that is, the smallest chip area required for VLSI implementation.

FAULT-TOLERANT COMMUNICATIONS ON HYPERCUBE-CLUSTERS

2000 ◽  
Vol 01 (04) ◽  
pp. 315-329 ◽  
Author(s):  
PETER KOK KEONG LOH ◽  
WEN JING HSU
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Cost Effective ◽  
Hardware Support ◽  
Tolerance Level ◽  
Component Faults ◽  
Message Overhead ◽  
Standard Components

Hierarchical interconnection networks with n-dimensional hypercube clusters can strike a balance between wide application suitability, size scalability as well as reliability. Cluster communications support for such networks must therefore be reliable and efficient without incurring large overheads. This paper proposes a reliable and cost-effective intra-cluster communications strategy for such a class of interconnection networks. The routing algorithm can tolerate up to (n - 1) component faults in the cluster and generates routes that are cycle-free and livelock-free. The message is guaranteed to be optimally (respectively, sub-optimally) delivered within a maximum of n (respectively, 2n - 1) hops. The message overhead incurred is one of the lowest reported for the specified fault tolerance level – with only a single n-bit routing vector accompanying the message to be communicated. Finally, routing hardware support may be simply achieved with standard components, facilitating integration with the host network.

scholarly journals Hierarchical Hexagon: A New Fault-Tolerant Interconnection Network for Parallel Systems

2021 ◽  
Vol 21 (1) ◽  
pp. 32-49
Author(s):  
Laxminath Tripathy ◽  
Chita Ranjan Tripathy
Keyword(s):  
Fault Tolerance ◽  
Hamiltonian Cycle ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Parallel Systems ◽  
Node Degree ◽  
Topological Parameters ◽  
Massively Parallel Systems ◽  
Network Cost ◽  
Hypercube Networks

Abstract A new interconnection network topology called Hierarchical Hexagon HH(n) is proposed for massively parallel systems. The new network uses a hexagon as the primary building block and grows hierarchically. Our proposed network is shown to be superior to the star based and the hypercube networks, with respect to node degree, diameter, network cost, and fault tolerance. We thoroughly analyze different topological parameters of the proposed topology including fault tolerance routing and embedding Hamiltonian cycle.

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