An Introduction to Multi-Core System on Chip – Trends and Challenges

2010 ◽  
pp. 1-21 ◽  
Author(s):  
Lionel Torres ◽  
Pascal Benoit ◽  
Gilles Sassatelli ◽  
Michel Robert ◽  
Fabien Clermidy ◽  
...  
Keyword(s):  
System On Chip ◽  
Core System ◽  
On Chip

Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)

2010 ◽  
Vol 34 (2-4) ◽  
pp. 102-116 ◽  
Author(s):  
Hyun-min Kyung ◽  
Gi-ho Park ◽  
Jong Wook Kwak ◽  
Tae-jin Kim ◽  
Sung-Bae Park
Keyword(s):  
Performance Analysis ◽  
System On Chip ◽  
Core System ◽  
Design And Implementation ◽  
On Chip

Heterogenic Multi-Core System on Chip for Virtual Based Security

2019 ◽  
Author(s):  
Vladimir Ruchkin ◽  
Vladimir Fulin ◽  
Dmitry Pikulin ◽  
Aleksandr Taganov ◽  
Aleksandr Kolesenkov ◽  
...  
Keyword(s):  
System On Chip ◽  
Core System ◽  
On Chip

scholarly journals FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip

2018 ◽  
Vol 7 (2.16) ◽  
pp. 57
Author(s):  
G Prasad Acharya ◽  
M Asha Rani
Keyword(s):  
Computer Aided Design ◽  
Processing System ◽  
System On Chip ◽  
Core System ◽  
Design Cycle ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Aided Design ◽  
Level Parallelism

The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.  

scholarly journals SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation

2013 ◽  
Vol 48 (8) ◽  
pp. 1943-1953 ◽  
Author(s):  
Eustace Painkras ◽  
Luis A. Plana ◽  
Jim Garside ◽  
Steve Temple ◽  
Francesco Galluppi ◽  
...  
Keyword(s):  
Neural Network ◽  
Network Simulation ◽  
System On Chip ◽  
Massively Parallel ◽  
Core System ◽  
Neural Network Simulation ◽  
On Chip

A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture

Integration ◽  
2015 ◽  
Vol 48 ◽  
pp. 55-71 ◽  
Author(s):  
Julius von Rosen ◽  
Felix Salfelder ◽  
Lars Hedrich ◽  
Benjamin Betting ◽  
Uwe Brinkschulte
Keyword(s):  
System On Chip ◽  
Core System ◽  
Mixed Signal ◽  
On Chip ◽  
Self Adaptive

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

2017 ◽  
Vol 54 ◽  
pp. 60-74 ◽  
Author(s):  
Alireza Monemi ◽  
Jia Wei Tang ◽  
Maurizio Palesi ◽  
Muhammad N. Marsono
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Core System ◽  
On Chip ◽  
Many Core

A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision

2016 ◽  
Author(s):  
Antonio Pullini ◽  
Francesco Conti ◽  
Davide Rossi ◽  
Igor Loi ◽  
Michael Gautschi ◽  
...  
Keyword(s):  
Energy Efficient ◽  
System On Chip ◽  
Core System ◽  
On Chip

Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs

2016 ◽  
Author(s):  
Zheng Wang ◽  
Alessandro Littarru ◽  
Emmanuel Ikechukwu Ugwu ◽  
Shazia Kanwal ◽  
Anupam Chattopadhyay
Keyword(s):  
Fault Tolerant ◽  
System On Chip ◽  
Chip Design ◽  
Core System ◽  
On Chip ◽  
Many Core
Sign in / Sign up

Export Citation Format

Share Document