Effective Trellis Decoding Techniques for Block Codes

1997 ◽  
pp. 37-44
Author(s):  
L. E. Aguado Bayón ◽  
P. G. Farrell
Keyword(s):  
Block Codes ◽  
Trellis Decoding

Trellis Decoding of Block Codes

1997 ◽  
Author(s):  
Bahram Honary ◽  
Garik Markarian
Keyword(s):  
Block Codes ◽  
Trellis Decoding

Scarce-state-transition error-trellis decoding of block codes with BPSK signals

1994 ◽  
Vol 30 (14) ◽  
pp. 1120-1121
Author(s):  
L.H.C. Lee ◽  
L.W. Lee
Keyword(s):  
State Transition ◽  
Block Codes ◽  
Trellis Decoding

Iterative maximum-likelihood trellis decoding for block codes

1999 ◽  
Vol 47 (3) ◽  
pp. 338-342 ◽  
Author(s):  
A.A. Luna ◽  
F.M. Fontaine ◽  
S.B. Wicker
Keyword(s):  
Maximum Likelihood ◽  
Block Codes ◽  
Trellis Decoding ◽  
Iterative Maximum Likelihood

scholarly journals FPGA implementation of trellis decoders for linear block codes

2014 ◽  
Vol 12 ◽  
pp. 61-67
Author(s):  
S. Scholl ◽  
E. Leonardi ◽  
N. Wehn
Keyword(s):  
Forward Error Correction ◽  
Convolutional Codes ◽  
Block Codes ◽  
Point Of View ◽  
Linear Block Codes ◽  
Banyan Network ◽  
Hardware Architectures ◽  
Trellis Decoding ◽  
Forward Error ◽  
First Time

Abstract. Forward error correction based on trellises has been widely adopted for convolutional codes. Because of their efficiency, they have also gained a lot of interest from a theoretic and algorithm point of view for the decoding of block codes. In this paper we present for the first time hardware architectures and implementations for trellis decoding of block codes. A key feature is the use of a sophisticated permutation network, the Banyan network, to implement the time varying structure of the trellis. We have implemented the Viterbi and the max-log-MAP algorithm in different folded versions on a Xilinx Virtex 6 FPGA.

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