High-Speed Viterbi Decoder

The Viterbi algorithm is the most well-known trellis-based maximum likelihood decoding algorithm. Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is implemented with a Viterbi decoder. High-speed applications require high-speed Viterbi decoders. Therefore, many hardware solutions have been proposed to improve the performance of Viterbi decoders. These hardware solutions explore the properties of the Viterbi algorithm to simplify and improve the architecture of the decoder. In particular, statistical properties of the algorithm are used to design parallel Viterbi decoders with very high data decoding rates. The article focuses on the implementation of high-speed Viterbi decoders.

Viterbi Decoder in Hardware

Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is the most well-known trellis-based maximum likelihood decoding algorithm. The Viterbi algorithm is executed by a Viterbi decoder. Different hardware solutions may be considered to implement a Viterbi decoder with different design requirements in terms of area, performance, power consumption, among others. The most appropriate solution depends on the metric requirements of the application as well as on the target technology. Properties of the Viterbi algorithm are used to simplify and improve the architecture of the Viterbi decoder. In particular, statistical properties of the Viterbi algorithm are used to design parallel Viterbi decoders with very high data decoding rates. The chapter focuses on the implementation of a Viterbi decoder in hardware, including optimizations to improve the area and performance.

Viterbi Decoder in Hardware

Trellis decoding is used to recover encoded information that was corrupted during transmission over a noisy channel. The Viterbi algorithm is the most well known trellis-based maximum likelihood decoding algorithm. The Viterbi algorithm is executed by a Viterbi decoder. Different hardware solutions may be considered to implement a Viterbi decoder with different design requirements in terms of area, performance, power consumption, among others. The most appropriate solution depends on the metric requirements of the application as well as on the target technology. Properties of the Viterbi algorithm are used to simplify and improve the architecture of the Viterbi decoder. In particular, statistical properties of the Viterbi algorithm are used to design parallel Viterbi decoders with very high data decoding rates. The article focuses on the implementation of a Viterbi decoder in hardware, including optimizations to improve the area and performance.

FPGA implementation of trellis decoders for linear block codes

Forward error correction based on trellises has been widely adopted for convolutional codes. Because of their efficiency, they have also gained a lot of interest from a theoretic and algorithm point of view for the decoding of block codes. In this paper we present for the first time hardware architectures and implementations for trellis decoding of block codes. A key feature is the use of a sophisticated permutation network, the Banyan network, to implement the time varying structure of the trellis. We have implemented the Viterbi and the max-log-MAP algorithm in different folded versions on a Xilinx Virtex 6 FPGA.