Towards Application-Centric Parallel Memories

2018 ◽  
pp. 481-493 ◽  
Author(s):  
Giulio Stramondo ◽  
Cătălin Bogdan Ciobanu ◽  
Ana Lucia Varbanescu ◽  
Cees de Laat
Keyword(s):  
Parallel Memories

HLS Support for Polymorphic Parallel Memories

2018 ◽  
Author(s):  
L. Stornaiuolo ◽  
M. Rabozzi ◽  
D. Sciuto ◽  
M. D. Santambrogio ◽  
G. Stramondo ◽  
...  
Keyword(s):  
Parallel Memories

scholarly journals Designing and building application‐centric parallel memories

2019 ◽  
Vol 32 (15) ◽  
Author(s):  
Giulio Stramondo ◽  
Cătălin Bogdan Ciobanu ◽  
Cees Laat ◽  
Ana Lucia Varbanescu
Keyword(s):  
Parallel Memories

On the Effective Bandwidth of Parallel Memories

1977 ◽  
Vol C-26 (5) ◽  
pp. 480-490 ◽  
Author(s):  
Chang ◽  
Kuck ◽  
Lawrie
Keyword(s):  
Effective Bandwidth ◽  
Parallel Memories

scholarly journals The Reduceron reconfigured and re-evaluated

2012 ◽  
Vol 22 (4-5) ◽  
pp. 574-613 ◽  
Author(s):  
MATTHEW NAYLOR ◽  
COLIN RUNCIMAN
Keyword(s):  
Reconfigurable Hardware ◽  
Functional Language ◽  
Language Implementation ◽  
Time Performance ◽  
Risc Processor ◽  
Dynamic Analyses ◽  
Parallel Memories ◽  
Run Time

AbstractA new version of a special-purpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.

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