CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme

Number theoretic transform (NTT) is widely utilized to speed up polynomial multiplication, which is the critical computation bottleneck in a lot of cryptographic algorithms like lattice-based post-quantum cryptography (PQC) and homomorphic encryption (HE). One of the tendency for NTT hardware architecture is to support diverse security parameters and meet resource constraints on different computing platforms. Thus flexibility and Area-Time Product (ATP) become two crucial metrics in NTT hardware design. The flexibility of NTT in terms of different vector sizes and moduli can be obtained directly. Whereas the varying strides in memory access of in-place NTT render the design for different radix and number of parallel butterfly units a tough problem. This paper proposes an efficient conflict-free memory mapping scheme that supports the configuration for both multiple parallel butterfly units and arbitrary radix of NTT. Compared to other approaches, this scheme owns broader applicability and facilitates the parallelization of non-radix-2 NTT hardware design. Based on this scheme, we propose a scalable radix-2 and radix-4 NTT multiplication architecture by algorithm-hardware co-design. A dedicated schedule method is leveraged to reduce the number of modular additions/subtractions and modular multiplications in radix-4 butterfly unit by 20% and 33%, respectively. To avoid the bit-reversed cost and save memory footprint in arbitrary radix NTT/INTT, we put forward a general method by rearranging the loop structure and reusing the twiddle factors. The hardware-level optimization is achieved by excavating the symmetric operators in radix-4 butterfly unit, which saves almost 50% hardware resources compared to a straightforward implementation. Through experimental results and theoretical analysis, we point out that the radix-4 NTT with the same number of parallel butterfly units outperforms the radix-2 NTT in terms of area-time performance in the interleaved memory system. This advantage is enlarged when increasing the number of parallel butterfly units. For example, when processing 1024 14-bit points NTT with 8 parallel butterfly units, the ATP of LUT/FF/DSP/BRAM n radix-4 NTT core is approximately 2.2 × /1.2 × /1.1 × /1.9 × less than that of the radix-2 NTT core on a similar FPGA platform.

Secure Deduplication For Cloud Storage Using Memory Mapping Technique For Improving Performance And Security

Data deduplication is a crucial technique for packing data and reducing duplication when transferring data. It is widely used in the cloud to restrict the usage of capacity memory and aids in transmission capacity sparing. Before redistributing data, an encryption mechanism is used to ensure the integrity of sensitive data during the deduplication process. The SHA algorithm is being used to save data in text format. To generate the security bits, padding is appended to the text. In de-duplication, it calculates the hash, i.e. hexadecimal number, string, and integer data. Hash-based de-duplication is the implementation of whole file hashing to the entire file. Text data’s hash values are considered to as feature properties. In contrast to traditional deduplication solutions, clients that transfer data to the cloud certify duplication inside the cloud data. In virtualization, both limiting primary memory size and memory blockage are considered important bottlenecks. Memory deduplication identifies pages with the same content and merges them into a single data file, reducing memory usage, memory parceling, and improving execution. In cloud storage, the MPT is used to deduplication so that it is used in single copies of the same data for different data owners. If any data users try to replicate the same data, it will be mapped and related to the archive data, implying that the data can’t be stored away. To ensure cloud data security, encryption techniques are used to encrypt data throughout deduplication procedures and prior to outsourcing cloud data.

Remote Access NVMe SSD via NTB

NVMe SSDs are deployed in data centers for applications with high performance, but its capacity and bandwidth are often underutilized. Remote access NVMe SSD enables flexible scaling and high utilization of Flash capacity and bandwidth within data centers. The current issue of remote access NVMe SSD has significant performance overheads. The research focuses on remote access NVMe SSD via NTB (non-transparent bridge). NTB is a type of PCI-Express; its memory mapping technology can allow to access memory belonging to peer servers. NVMe SSD supports multiple I/O queues to maximize the I/O parallel processing of flash; hence, NVMe SSD can provide significant performance when comparing with traditional hard drives. The research proposes a novel design based on features of NTB memory mapping and NVMe SSD multiple I/O queues. The remote and local servers can access the same NVMe SSD concurrently. The experimental results show the performance of remote access NVMe SSD can approach the local access. It is significantly excellent and proved feasible.

Placeless and barrier-free? Connecting place memories online within an unequal society

Digital media have a significant impact on how individuals and groups relate to their own as well as shared memories. Digital and online memorialisation has the potential to connect a greater number of disparate agents across physical place boundaries. Using the case study of an online mapping project recording women’s migration experiences, this article finds that digital media are indeed used to challenge established place narratives and contest an exclusionary sense of place. This online memory mapping is intended to connect personal memories of local areas across group and place boundaries. Thematic tagging serves as a tool to connect local memories globally. However, these attempts are situated within an unequal society, where resources, time and digital skills are not equally available to all. Offline power relations and social location are thus found to be constitutive of the making of online memory maps and to hinder democratised memory-making of place.

VolPy: Automated and scalable analysis pipelines for voltage imaging datasets

Voltage imaging enables monitoring neural activity at sub-millisecond and sub-cellular scale, unlocking the study of subthreshold activity, synchrony, and network dynamics with unprecedented spatio-temporal resolution. However, high data rates (>800MB/s) and low signal-to-noise ratios create bottlenecks for analyzing such datasets. Here we present VolPy, an automated and scalable pipeline to pre-process voltage imaging datasets. VolPy features motion correction, memory mapping, automated segmentation, denoising and spike extraction, all built on a highly parallelizable, modular, and extensible framework optimized for memory and speed. To aid automated segmentation, we introduce a corpus of 24 manually annotated datasets from different preparations, brain areas and voltage indicators. We benchmark VolPy against ground truth segmentation, simulations and electrophysiology recordings, and we compare its performance with existing algorithms in detecting spikes. Our results indicate that VolPy’s performance in spike extraction and scalability are state-of-the-art.

Cybercartography and education: research and teaching with the Residential Schools Land Memory Atlas

This paper sheds light on intersections between teaching and research in the Cybercartographic Residential Schools Land Memory Atlas (RSLMA), which is the central output of the Residential Schools Land Memory Mapping Project (RSLMMP). Building on previous work in Cybercartography, the RSLMMP has further contributed to the integration of research and education and the emergence of new research and education relationships. Viewing the atlas as a project output comprised of iterative processes along multiple dimensions allows us to appreciate limitations as challenges for further iterations, including new related projects and ongoing volunteer work with students. In addition to participating in the national response to the Truth and Reconciliation Commission of Canada’s Calls to Action, this project – including the atlas – provides a model for a unique blend of teaching and research and the basis for further and new collaborations with a variety of different partners, including Residential School survivors. As a reconciliation project, the Residential Schools Land Memory Atlas further contributes to the intercultural bridge building aims of its parent, the Lake Huron Treaty Atlas, as it forges on in new directions.

Reconfiguring the traditional knowledge system for providing earthquake resistance: The case of post-disaster reconstruction of Khokana Village, Nepal

Cultural landscapes represent a closely woven net of inter-relationships between people, events and places over time; they are a symbol of the growing recognition of the fundamental links between local communities and their heritage, between people and their natural environment, and are hence crucial to their identity. In architectural projects like post-disaster reconstruction, which revolves around the needs of the communities decimated by a disaster, decisions taken become especially critical, as they have a long-term impact on the community and its built environment. It therefore requires one to take into account the cultural, social, and environmental context. This paper considers the case of Khokana, a traditional Newari settlement in the Kathmandu valley, in order to study its spatial configuration, determined by its socio-cultural activities, through the lens of collective memory mapping. It further analyzes the repercussions on the intangible values and tangible built environment of the community following the 2015 Nepal earthquake, and proposes a new design approach based on an understanding of Khokana’s traditional knowledge system and practices. Finally, we propose a model to achieve community resilience while keeping the community’s values and spatial ethos intact.

SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput

In-memory processing can dramatically improve the latency and energy consumption of computing systems by minimizing the data transfer between the memory and the processor. Efficient execution of processing operations within the memory is therefore a highly motivated objective in modern computer architecture. This paper presents a novel automatic framework for efficient implementation of arbitrary combinational logic functions within a memristive memory. Using tools from logic design, graph theory and compiler register allocation technology, we developed SIMPLER (Synthesis and In-memory MaPping of Logic Execution in a single Row), a tool that optimizes the execution of in-memory logic operations in terms of throughput and area. Given a logical function, SIMPLER automatically generates a sequence of atomic Memristor-Aided loGIC (MAGIC) NOR operations and efficiently locates them within a single size-limited memory row, reusing cells to save area when needed. This approach fully exploits the parallelism offered by the MAGIC NOR gates. It allows multiple instances of the logic function to be performed concurrently, each compressed into a single row of the memory. This virtue makes SIMPLER an attractive candidate for designing in-memory Single Instruction, Multiple Data (SIMD) operations. Compared to previous work (that optimizes latency rather than throughput for a single function), SIMPLER achieves an average throughput improvement of 435×. When previous tools are parallelized similarly to SIMPLER, SIMPLER achieves higher throughput of at least 5×, with 23× improvement in area and 20× improvement in area efficiency. These improvements more than fully compensate for the increase (up to 17% on average) in latency.