The Reduceron reconfigured and re-evaluated
2012 ◽
Vol 22
(4-5)
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pp. 574-613
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Keyword(s):
AbstractA new version of a special-purpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.
2002 ◽
Vol 2
(6)
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pp. 769-805
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Keyword(s):