Formal Timing Analysis of Digital Circuits

2019 ◽  
pp. 84-100
Author(s):  
Qurat Ul Ain ◽  
Osman Hasan
Keyword(s):  
Digital Circuits ◽  
Timing Analysis

scholarly journals Matlab Interface For Power And Timing Analysis Of Digital Circuits

2017 ◽  
Vol 3 (1) ◽  
pp. 8-17
Author(s):  
Gaurav Verma ◽  
Sourav Abhishek ◽  
Abhishek Chauhan ◽  
Anushka Singh ◽  
Manya Mehta
Keyword(s):  
Digital Circuits ◽  
Timing Analysis

Test Approach Based on Decision Diagrams for Delay Fault Caused by Crosstalk Interferences in Digital Circuits

2010 ◽  
Vol 663-665 ◽  
pp. 559-562
Author(s):  
Zhong Liang Pan ◽  
Ling Chen
Keyword(s):  
Digital Circuits ◽  
Timing Analysis ◽  
Decision Diagrams ◽  
Delay Faults ◽  
Static Timing Analysis ◽  
Technology Scaling ◽  
Static Timing ◽  
Delay Sensitive ◽  
Test Vectors ◽  
Selection Of

The crosstalk is induced between the elements in digital circuits due the increasing switching speeds and the decreasing in technology scaling. The crosstalk is caused by parasitic couplings between adjacent wires that include capacitance and inductance effects. The crosstalk can result in functional failures or timing problems. A test approach for the delay faults caused by crosstalk interferences in digital circuits is presented in this paper, the approach is based on decision diagrams and the selection of delay sensitive path. The static timing analysis is carried out to obtain the delay information about the paths, all aggressor lines are activated in the best possible way. The test vectors are generated by building a decision diagram and searching for the specific paths in the decision diagram. Experimental results show that the test approach proposed in this paper can generate the test vectors for the testable delay faults caused by crosstalk.

scholarly journals Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis

VLSI Design ◽  
2002 ◽  
Vol 15 (3) ◽  
pp. 647-666 ◽  
Author(s):  
Tong Xiao ◽  
Malgorzata Marek-Sadowska
Keyword(s):  
Digital Circuits ◽  
Timing Analysis ◽  
Deep Submicron ◽  
Functional Information ◽  
Slew Rate ◽  
Static Timing Analysis ◽  
Circuit Performance ◽  
Arrival Times ◽  
Static Timing ◽  
Functional Correlation

Crosstalk-induced delay in deep sub-micron digital circuits can be quite significant and difficult to determine because of dependency on neighboring signals. In this paper we study the problem of incorporating temporal and functional information to improve the accuracy of crosstalk aware static timing analysis. We propose an efficient method to compute a signal's earliest and latest arrival times when timing windows and slew rate ranges are known for its inputs and its coupling neighbors' inputs. We show that iteratively updating timing windows is necessary when signals on the same path are mutually coupled. The accuracy of static timing analysis can be further improved by our functional correlation analysis. The proposed techniques have been applied in crosstalk aware static timing analysis, which can guide timing-driven layout synthesis and quick timing verification in deep submicron technologies. Experimental results demonstrate that the proposed methods significantly reduce the pessimism in predicting circuit performance.

Sign in / Sign up

Export Citation Format

Share Document