Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices

As the technology scaling advances, limitations of traditional memories in terms of density and energy become more evident. Modern caches occupy a large part of a CPU physical size and high static leakage poses a limit to the overall efficiency of the systems, including IoT/edge devices. Several alternatives to CMOS SRAM memories have been studied during the past few decades, some of which already represent a viable replacement for different levels of the cache hierarchy. One of the most promising technologies is the spin-transfer torque magnetic RAM (STT-MRAM), due to its small basic cell design, almost absent static current and non-volatility as an added value. However, nothing comes for free, and designers will have to deal with other limitations, such as the higher latencies and dynamic energy consumption for write operations compared to reads. The goal of this work is to explore several microarchitectural parameters that may overcome some of those drawbacks when using STT-MRAM as last-level cache (LLC) in embedded devices. Such parameters include: number of cache banks, number of miss status handling registers (MSHRs) and write buffer entries, presence of hardware prefetchers. We show that an effective tuning of those parameters may virtually remove any performance loss while saving more than 60% of the LLC energy on average. The analysis is then extended comparing the energy results from calibrated technology models with data obtained with freely available tools, highlighting the importance of using accurate models for architectural exploration.

OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems

With technology scaling, maintaining the reliability of dynamic random-access memory (DRAM) has become more challenging. Therefore, on-die error correction codes have been introduced to accommodate reliability issues in DDR5. However, the current solution still suffers from high overhead when a large DRAM capacity is used to deliver high performance. We present a DRAM chip architecture that can track faults at byte-level DRAM cell errors to address this problem. DRAM faults are classified as temporary or permanent in our proposed architecture, with no additional pins and with minor DRAM chip modifications. Hence, we achieve reliability comparable to that of other state-of-the-art solutions while incurring negligible performance and energy overhead. Furthermore, the faulty locations are efficiently exposed to the operating system (OS). Thus, we can significantly reduce the required scrubbing cycle by scrubbing only faulty DRAM pages while reducing the system failure probability up to 5000∼7000 times relative to conventional operation.

Advances in traceability systems in agri-food supply chains

Failure to deliver safe and high-quality food reduces consumer confidence in the food industry and results in costly food crises, foodborne illnesses and disruption to food supply chains. Recent advances in traceability systems, and associated identification and communication technologies hold the potential to ensure food quality and safety by managing effective traceability throughout the food supply chains. However, deficits in various factors e.g., resources, awareness, training, standards, data management and technology scaling impede exploitation of these cutting-edge traceability technologies. This chapter provides a review of the advances in agri-food traceability systems and technologies, barriers to their implementations, and possible improvement pathways and policy interventions to promote deployment of advanced food traceability systems.

Revisiting Symptom-Based Fault Tolerant Techniques against Soft Errors

Aggressive technology scaling and near-threshold computing have made soft error reliability one of the leading design considerations in modern embedded microprocessors. Although traditional hardware/software redundancy-based schemes can provide a high level of protection, they incur significant overheads in terms of performance and hardware resources. The considerable overheads from such full redundancy-based techniques has motivated researchers to propose low-cost soft error protection schemes, such as symptom-based error protection schemes. The main idea behind a symptom-based error protection scheme is that soft errors in the system will quickly generate some symptoms, such as exceptions, branch mispredictions, cache or TLB misses, or unpredictable variable values. Therefore, monitoring such infrequent symptoms makes it possible to cover the manifestation of failures caused by soft errors. Symptom-based protection schemes have been suggested as shortcuts to achieve acceptable reliability with comparable overheads. Since the symptom-based protection schemes seem attractive due to their generality and simplicity, even state-of-the-art protection schemes exploit them as the baseline protections. However, our detailed analysis of the fault coverage and performance overheads of such schemes reveals that the user-visible failure coverage, particularly of ReStore, is limited (29% on average). By contrast, the runtime overheads are significant (40% on average) because the majority of the fault injection experiments, which were considered as detected/recovered failures by low-level symptoms, are actually benign faults by program-level masking effects.

Genetic Algorithm-Based Digital Test Optimization Method and its Application to Yield Improvement

Narrowing design and manufacturing process margins with technology scaling are one of the causes for a reduction in IC chip test margin. This situation is further aggravated by the extensive use of third-party design blocks in contemporary system-on-chips which complicates chip timing constraint. Since a thorough timing verification prior to silicon fabrication is usually not done due to aggressive product launch schedules and escalating design cost, occasionally, a post-silicon timing optimization process is required to eliminate false fails encountered on ATE. An iterative two-dimensional shmoo plots and pin margin analysis are custom optimization methods to accomplish this. However, these methods neglect the interdependencies between different IO timing edges such that a truly optimized condition cannot be attained. In this paper, we present a robust and automated solution based on a genetic algorithm approach. Elimination of shmoo holes and widening of test margins (up to 2x enhancements) are demonstrated on actual product test cases. Besides test margin optimization, this method also offers insights into the criticality of test pins to accelerate failure debug turnaround time.

Performance And Reliability Improvement In Intercalated MLGNR Interconnects Using Optimized Aspect Ratio

In this work, aspect ratio of various intercalation doped MLGNR interconnects are optimized using a numerical approach toachieve improved performance and reliability. A numerical optimization method is presented to estimate optimized aspect ratio considering combined effects of performance, noise and reliability metrics for any arbitrary nano interconnect system. This approach is cost effective and will be extremely useful to industry for selection of aspect ratio of interconnects as it is a non-SPICE method and reduces fabrication iterations for achieving desired performance and reliability. Our numerical method suggests that by minimizing the figure of merit (i.e. Noise Delay Power Product (NPDP) / Breakdown Power PBD ratio), aspect ratio of FeCl3 doped MLGNR interconnect is optimized at 0.987, 0.61 and 0.579 for local, intermediate and global level, respectively at 7 nm node. Comparing the optimized performance metrics in this work with the estimated metrics at prescribed aspect ratio by IRDS roadmap, delay, noise delay product (NDP), power delay product (PDP), PDP/PBD ratio and figure of meritare improved by (∼2% and ∼25%), (∼44% and ∼50%), (∼9% and ∼48%), (∼6% and ∼48%) and (∼49% and ∼68%) for 10 µm and 1 mm long FeCl3 doped MLGNR interconnect, respectively at 7 nm node. Increase in contact resistance leads to significant decrease in performance and increase in optimized aspect ratio of local FeCl3 doped MLGNR interconnect. Scaling down from 10 nm to 7 nm node results in increase of optimized aspect ratio in all levels of interconnects. Even though theperformance of MLGNR degrades with scaling down but when compared to copper, the performance improves with technology scaling. Finally, this study provides circuit designers a detailed guideline for selecting an optimized aspect ratio for achieving better performance, power efficiency and reliability in doped MLGNR interconnects.

Adaptive Spiking Sensor System Based on CMOS Memristors Emulating Long and Short-Term Plasticity of Biological Synapses for Industry 4.0 Applications

A conventional analog to digital converter (ADC) faces many issues with leading-edge technologies due to noise, manufacturing deviations, signal swings, etc. Thus, we pursue to design an adaptive spiking neural ADC (SN-ADC) with promising features, e.g., robust to noise, low-power, technology scaling issues, and low-voltage operation. Therefore, our approach promises to be technology agnostic, i.e., effectively translatable to aggressive new technologies. It supports machine learning and self-x (self-calibration, self-healing) that needs for industry 4.0 and the internet of things (IoTs). In this work, we design an adaptive spike-to-rank coding (ASRC), which is the main part of the spiking neural ADC. The ASRC is based on CMOS memristors emulating short-term plasticity (STP) and long-term plasticity (LTP) biological synapses. The proposed ASRC compensates deviations by adapting the weights of the synapses. Also, ASRC is designed using XFAB 0.35 μm CMOS technology and Cadence design tools. In addition, ASRC is simulated to test its performance in the temperature range (−40°C to 85°C).