Dependency Graph-based High-level Synthesis for Maximum Instruction Parallelism

Performance optimization is an important goal for High-level Synthesis (HLS). Existing HLS scheduling algorithms are all based on Control and Data Flow Graph (CDFG) and will schedule basic blocks in sequential order. Our study shows that the sequential scheduling order of basic blocks is a big limiting factor for achievable circuit performance. In this article, we propose a Dependency Graph (DG) with two important properties for scheduling. First, DG is a directed acyclic graph. Thus, no loop breaking heuristic is needed for scheduling. Second, DG can be used to identify the exact instruction parallelism. Our experiment shows that DG can lead to 76% instruction parallelism increase over CDFG. Based on DG, we propose a bottom-up scheduling algorithm to achieve much higher instruction parallelism than existing algorithms. Hierarchical state transition graph with guard conditions is proposed for efficient implementation of such high parallelism scheduling. Our experimental results show that our DG-based HLS algorithm can outperform the CDFG-based LegUp and the state-of-the-art industrial tool Vivado HLS by 2.88× and 1.29× on circuit latency, respectively.

Self-heating effect on logic performance of 6T-SRAM based on CFET device

CFET devices have become emerging and promising candidates for continuing Moore's law at sub-3 nm nodes owing to the area advantage of the N-P stacked structure, which markedly improves the integration of circuits. However, the introduction of vertical structure leads to severe thermal issues due to the self-heating effect, resulting in the degradation of the device and circuit performance. This paper mainly evaluates and analyzes the performance of the SRAM unit built using the CFET structure. The CFET-SRAM exhibits better performance than the conventional CMOS-SRAM in terms of access delay, even with the impact of self-heating. For the multi-fin-based CFET, although the total gate capacitance increases, the enhanced current improves the static noise margin significantly. However, as the number of channels expands, sheet-based CFET devices show more comprehensive superiority of area and performance.

Mutual inductance of two coaxial rectangular PCB coils incorporating magnetic layer

The wireless connection distance between the transmission and reception coils of printed circuit boards (PCB) influences the mutual inductance and affects circuit performance. In this study, the mutual inductance M of PCB coils was investigated, and two analytical methods were presented for calculating the mutual inductance between two coaxial rectangular planar PCB coils incorporating magnetic layer. The results were acquired through calculations by using the Neumann integral and Biot-Savart methods. The complete integral calculations and detailed demonstrations of the two methods are presented. The obtained formulas were introduced in some examples of coils with different number of turns. The analytical and experimental results were compared, and a strong agreement between them was observed.

Countering the Deleterious Effects of Electromagnetic Pulse

Robot systems like automated shipping swinging robots, wire transducer sensors and even computer indigenous time sensors (amongst others) often use oscillating circuits such as the famous van der Pol system, while this manuscript investigates protection of such sensor circuitry to spurious voltage spikes accompanying an electromagnetic pulse. These spurious voltages can lead to uncontrolled robot motion and even debilitation. A very brief discussion of electromagnetic pulses yields design parameters to evaluate circuit responses to realistic disturbing pulses. Recent research in nonlinear-adaptive methods to protect circuits are described to highlight the proposed novelty: utilization of feedback rules as adaptive mechanisms to modify the otherwise nonlinear feedforwards systems improving the results in recent literature. Feedback is iterated to select adaption parameters that simultaneously produce favorable circuit performance in addition to effective parameter identification inherent in the adaption (to provide meaningful parameter estimates to unspecified future applications). Spurious voltages were rapidly rejected with a mere 0.3% trajectory deviation, stabilizing quickly with a final (steady state) deviation of 0.01%. The demonstrated abilities to reject the deleterious spurious effects are compared to nominal figures of merit for timing accuracy of various computer systems to conclude the proposed methods are effective for some applications, but insufficient for others.

Ternary logic decoder using independently controlled double-gate Si-NW MOSFETs

A ternary logic decoder (TLD) is demonstrated with independently controlled double-gate (ICDG) silicon-nanowire (Si-NW) MOSFETs to confirm a feasibility of mixed radix system (MRS). The TLD is essential component for realization of the MRS. The ICDG Si-NW MOSFET resolves the limitations of the conventional multi-threshold voltage (multi-Vth) schemes required for the TLD. The ICDG Si-NW MOSFETs were fabricated and characterized. Afterwards, their electrical characteristics were modeled and fitted semi-empirically with the aid of SILVACO ATLAS TCAD simulator. The circuit performance and power consumption of the TLD were analyzed using ATLAS mixed-mode TCAD simulations. The TLD showed a power-delay product of 35 aJ for a gate length (LG) of 500 nm and that of 0.16 aJ for LG of 14 nm. Thanks to its inherent CMOS-compatibility and scalability, the TLD based on the ICDG Si-NW MOSFETs would be a promising candidate for a MRS using ternary and binary logic.

Semi-analytical modelling and evaluation of uniformly doped silicene nanotransistors for digital logic gates

Silicene has attracted remarkable attention in the semiconductor research community due to its silicon (Si) nature. It is predicted as one of the most promising candidates for the next generation nanoelectronic devices. In this paper, an efficient non-iterative technique is employed to create the SPICE models for p-type and n-type uniformly doped silicene field-effect transistors (FETs). The current-voltage characteristics show that the proposed silicene FET models exhibit high on-to-off current ratio under ballistic transport. In order to obtain practical digital logic timing diagrams, a parasitic load capacitance, which is dependent on the interconnect length, is attached at the output terminal of the logic circuits. Furthermore, the key circuit performance metrics, including the propagation delay, average power, power-delay product and energy-delay product of the proposed silicene-based logic gates are extracted and benchmarked with published results. The effects of the interconnect length to the propagation delay and average power are also investigated. The results of this work further envisage the uniformly doped silicene as a promising candidate for future nanoelectronic applications.