Soft Error Rate Estimation of VLSI Circuits

2020 ◽  
pp. 9-23
Author(s):  
Behnam Ghavami ◽  
Mohsen Raji
Keyword(s):  
Error Rate ◽  
Vlsi Circuits ◽  
Soft Error ◽  
Soft Error Rate ◽  
Rate Estimation

SOFT ERROR RATE ESTIMATION FOR COMBINATIONAL LOGIC IN PRESENCE OF SINGLE EVENT MULTIPLE TRANSIENTS

2014 ◽  
Vol 23 (06) ◽  
pp. 1450091 ◽  
Author(s):  
RAMIN RAJAEI ◽  
MAHMOUD TABANDEH ◽  
MAHDI FAZELI
Keyword(s):  
Error Rate ◽  
Radiation Effects ◽  
Fault Injection ◽  
Estimation Method ◽  
Accurate Method ◽  
Vlsi Circuits ◽  
Soft Error ◽  
Accurate Estimation ◽  
Fast Method ◽  
Soft Error Rate

Fast and accurate estimation of soft error rate in VLSI circuits is an essential step in a soft error tolerant ASIC design. In order to have a cost effective protection against radiation effects in combinational logics, an accurate and fast method for identification of most susceptive gates and paths is needed. In this paper, an efficient, fast and accurate method for soft error propagation probability (SEPP) estimation is presented and its performance is evaluated. This method takes into account all three masking factors in multi cycles. It also considers multiple event transients as a new challenge in soft error tolerant VLSI circuit design. Compared with Monte Carlo (MC) simulation-based fault injection method, our SEPP estimation method has a high level of accuracy (with less than 2% difference) while offering 1000× speedup as compared with MC-based simulation.

Sign in / Sign up

Export Citation Format

Share Document