Library-Based Attack Tree Synthesis

Graphical Models for Security - Lecture Notes in Computer Science ◽

10.1007/978-3-030-62230-5_2 ◽

2020 ◽

pp. 24-44

Author(s):

Sophie Pinchinat ◽

François Schwarzentruber ◽

Sébastien Lê Cong

Keyword(s):

Attack Tree ◽

Tree Synthesis

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Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

IEICE Transactions on Electronics ◽

10.1587/transele.e94.c.288 ◽

2011 ◽

Vol E94-C (3) ◽

pp. 288-295 ◽

Cited By ~ 6

Author(s):

Kazuyoshi TAKAGI ◽

Yuki ITO ◽

Shota TAKESHIMA ◽

Masamitsu TANAKA ◽

Naofumi TAKAGI

Keyword(s):

Clock Tree ◽

Clock Tree Synthesis ◽

Tree Synthesis

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Symmetrical Buffered Clock Tree Synthesis Considering NBTI

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180674 ◽

2020 ◽

Author(s):

Deokkeun Oh ◽

Mujun Choi ◽

Juho Kim

Keyword(s):

Clock Tree ◽

Clock Tree Synthesis ◽

Tree Synthesis

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Vulnerability Assessment of WAMS Communication System in the Energy Internet Based on Attack Tree Model

2020 IEEE Sustainable Power and Energy Conference (iSPEC) ◽

10.1109/ispec50848.2020.9351155 ◽

2020 ◽

Author(s):

Zhang Kai-lun ◽

Tang Quan ◽

Zhang Hong-gang

Keyword(s):

Vulnerability Assessment ◽

Communication System ◽

Tree Model ◽

Attack Tree ◽

Energy Internet

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Compressor tree synthesis on commercial high-performance FPGAs

ACM Transactions on Reconfigurable Technology and Systems ◽

10.1145/2068716.2068725 ◽

2011 ◽

Vol 4 (4) ◽

pp. 1-19 ◽

Cited By ~ 25

Author(s):

Hadi Parandeh-Afshar ◽

Arkosnato Neogy ◽

Philip Brisk ◽

Paolo Ienne

Keyword(s):

High Performance ◽

Tree Synthesis

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A Novel Attack Tree Based Risk Assessment Approach for Location Privacy Preservation in the VANETs

2011 IEEE International Conference on Communications (ICC) ◽

10.1109/icc.2011.5962947 ◽

2011 ◽

Cited By ~ 14

Author(s):

Dandan Ren ◽

Suguo Du ◽

Haojin Zhu

Keyword(s):

Risk Assessment ◽

Privacy Preservation ◽

Location Privacy ◽

Attack Tree ◽

Assessment Approach

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Wakeup scheduling and its buffered tree synthesis for power gating circuits

Integration ◽

10.1016/j.vlsi.2015.12.008 ◽

2016 ◽

Vol 53 ◽

pp. 157-170 ◽

Cited By ~ 1

Author(s):

Sangmin Kim ◽

Seungwhun Paik ◽

Seokhyeong Kang ◽

Youngsoo Shin

Keyword(s):

Power Gating ◽

Wakeup Scheduling ◽

Tree Synthesis

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Industrial Control System Intrusion Detection Model based on LSTM & Attack Tree

2020 17th International Computer Conference on Wavelet Active Media Technology and Information Processing (ICCWAMTIP) ◽

10.1109/iccwamtip51612.2020.9317477 ◽

2020 ◽

Author(s):

Fan Xingjie ◽

Wan Guogenp ◽

Zhang ShiBIN ◽

ChenHAO

Keyword(s):

Control System ◽

Intrusion Detection ◽

Industrial Control System ◽

Industrial Control ◽

Attack Tree ◽

Detection Model ◽

Model Based

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An OCV-Aware Clock Tree Synthesis Methodology

10.1109/iccad51958.2021.9643585 ◽

2021 ◽

Author(s):

Necati Uysal ◽

Rickard Ewetz

Keyword(s):

Clock Tree ◽

Clock Tree Synthesis ◽

Synthesis Methodology ◽

Tree Synthesis

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Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations

High Performance Clock Distribution Networks ◽

10.1007/978-1-4684-8440-3_4 ◽

1996 ◽

pp. 37-49 ◽

Cited By ~ 3

Author(s):

José Luis Neves ◽

Eby G. Friedman

Keyword(s):

Process Parameter ◽

Clock Skew ◽

Clock Tree ◽

Parameter Variations ◽

Clock Tree Synthesis ◽

Clock Skew Scheduling ◽

Tree Synthesis

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Technology transfer by means of fault tree synthesis

10.1063/1.4772100 ◽

2012 ◽

Author(s):

Dimitris F. Batzias

Keyword(s):

Technology Transfer ◽

Fault Tree ◽

Tree Synthesis

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