Papers in the literature dealing with the Ethernet network characterize packet delay variation (PDV) as a long-range dependence (LRD) process. Fractional Gaussian noise (fGn) or generalized fraction Gaussian noise (gfGn) belong to the LRD process. This paper proposes a novel clock skew estimator for the IEEE1588v2 applicable for the white-Gaussian, fGn, or gfGn environment. The clock skew estimator does not depend on the unknown asymmetry between the fixed delays in the forward and reverse paths nor on the clock offset between the Master and Slave. In addition, we supply a closed-form-approximated expression for the mean square error (MSE) related to our new proposed clock skew estimator. This expression is a function of the Hurst exponent H, as a function of the parameter a for the gfGn case, as a function of the total sent Sync messages, as a function of the Sync period, and as a function of the PDV variances of the forward and reverse paths. Simulation results confirm that our closed-form-approximated expression for the MSE indeed supplies the performance of our new proposed clock skew estimator efficiently for various values of the Hurst exponent, for the parameter a in gfGn case, for different Sync periods, for various values for the number of Sync periods and for various values for the PDV variances of the forward and reverse paths. Simulation results also show the advantage in the performance of our new proposed clock skew estimator compared to the literature known ML-like estimator (MLLE) that maximizes the likelihood function obtained based on a reduced subset of observations (the first and last timing stamps). This paper also presents designing graphs for the system designer that show the number of the Sync periods needed to get the required clock skew performance (MSE = 10–12). Thus, the system designer can approximately know in advance the total delay or the time the system has to wait until getting the required system’s performance from the MSE point of view.