A Novel Clock Skew Estimator and Its Performance for the IEEE 1588v2 (PTP) Case in Fractional Gaussian Noise/Generalized Fractional Gaussian Noise Environment

Papers in the literature dealing with the Ethernet network characterize packet delay variation (PDV) as a long-range dependence (LRD) process. Fractional Gaussian noise (fGn) or generalized fraction Gaussian noise (gfGn) belong to the LRD process. This paper proposes a novel clock skew estimator for the IEEE1588v2 applicable for the white-Gaussian, fGn, or gfGn environment. The clock skew estimator does not depend on the unknown asymmetry between the fixed delays in the forward and reverse paths nor on the clock offset between the Master and Slave. In addition, we supply a closed-form-approximated expression for the mean square error (MSE) related to our new proposed clock skew estimator. This expression is a function of the Hurst exponent H, as a function of the parameter a for the gfGn case, as a function of the total sent Sync messages, as a function of the Sync period, and as a function of the PDV variances of the forward and reverse paths. Simulation results confirm that our closed-form-approximated expression for the MSE indeed supplies the performance of our new proposed clock skew estimator efficiently for various values of the Hurst exponent, for the parameter a in gfGn case, for different Sync periods, for various values for the number of Sync periods and for various values for the PDV variances of the forward and reverse paths. Simulation results also show the advantage in the performance of our new proposed clock skew estimator compared to the literature known ML-like estimator (MLLE) that maximizes the likelihood function obtained based on a reduced subset of observations (the first and last timing stamps). This paper also presents designing graphs for the system designer that show the number of the Sync periods needed to get the required clock skew performance (MSE = 10–12). Thus, the system designer can approximately know in advance the total delay or the time the system has to wait until getting the required system’s performance from the MSE point of view.

A Low Energy Clock Network with a Huge Number of Local Synchronized Oscillators

<div>A clock system for a huge grid of small clock regions is presented. There is an oscillator in each clock region, which drives the local clock of a processing element (PE). The oscillators are kept synchronized by exploiting the phase of their neighbors. In an infinite mesh, the clock skew would be zero, but in a network of limited size there will be fringe effects. In a mesh with 25×25 oscillators, the maximum skew between neighboring regions is within 3.3 ps. By slightly adjusting the free running frequency of the oscillators, this skew can be reduced to 1.2 ps. The mesh may contain millions of clock regions.</div><div> Because there is no central clock, both power consumption and clock frequency can be improved compared to a conventional clock distribution network. A PE of 150×150 µm² running at 6.7 GHz with 93 master-slave flip-flops is used as an example. The PE-internal clock skew is less than 2.3 ps, and the energy consumption of the clock system 807 µW per PE. It corresponds to an effective gate and wire capacitance of 509 aF, or 7.3 gate capacitances.</div><div> Power noise is reduced by scheduling the local oscillators gradually along one of the grid’s axes. In this way, surge currents, which generally have their peaks at the clock edges, are distributed evenly over a full clock cycle.</div>

A Low Energy Clock Network with a Huge Number of Local Synchronized Oscillators

<div>A clock system for a huge grid of small clock regions is presented. There is an oscillator in each clock region, which drives the local clock of a processing element (PE). The oscillators are kept synchronized by exploiting the phase of their neighbors. In an infinite mesh, the clock skew would be zero, but in a network of limited size there will be fringe effects. In a mesh with 25×25 oscillators, the maximum skew between neighboring regions is within 3.3 ps. By slightly adjusting the free running frequency of the oscillators, this skew can be reduced to 1.2 ps. The mesh may contain millions of clock regions.</div><div> Because there is no central clock, both power consumption and clock frequency can be improved compared to a conventional clock distribution network. A PE of 150×150 µm² running at 6.7 GHz with 93 master-slave flip-flops is used as an example. The PE-internal clock skew is less than 2.3 ps, and the energy consumption of the clock system 807 µW per PE. It corresponds to an effective gate and wire capacitance of 509 aF, or 7.3 gate capacitances.</div><div> Power noise is reduced by scheduling the local oscillators gradually along one of the grid’s axes. In this way, surge currents, which generally have their peaks at the clock edges, are distributed evenly over a full clock cycle.</div>

A Solution to Design Semi-static Null Convention Logic Cell Libraries

The Null Convention Logic (NCL) based asynchronous circuits have eliminated the disadvantages of the synchronous circuits, including noise, glitches, clock skew, power, and electromagnetic interference. However, using NCL based asynchronous designs was not easy for students and researchers because of the lack of standard NCL cell libraries. This paper proposes a solution to design a semi-static NCL cell library used to synthesize NCL based asynchronous designs. This solution will help researchers save time and effort to approach a new method. In this work, NCL cells are designed based on the Process Design Kit 45nm technology. They are simulated at the different corners with the Ocean script and Electronic Design Automation (EDA) environment to extract the timing models and the power models. These models are used to generate a *.lib file, which is converted to a *.db file by the Design Compiler tool to form a complete library of 27 cells. In addition, we synthesize the NCL based full adders to illustrate the success of the proposed library and compare our synthesis results with the results of the other authors. The comparison results indicate that power and delay are improved significantly.

An Investigation of Clock Skew Using a Wirelength-Aware Floorplanning Process in the Pre-Placement Stages of MSV Layouts

Managing the timing constraints has become an important factor in the physical design of multiple supply voltage (MSV) integrated circuits (IC). Clock distribution and module scheduling are some of the conventional methods used to satisfy the timing constraints of a chip. In this paper, we propose a simulated annealing-based MSV floorplanning methodology for the design of ICs within the timing budget. Additionally, we propose a modified SKB tree representation for floorplanning the modules in the design. Our algorithm finds the optimal dimensions and position of the clocked modules in the design to reduce the wirelength and satisfy the timing constraints. The proposed algorithm is implemented in IWLS 2005 benchmark circuits and considers power, wirelength, and timing as the optimization parameters. Simulation results were obtained from the Cadence Innovus digital system taped-out at 45 nm. Our simulation results show that the proposed algorithm satisfies timing constraints through a 30.6% reduction in wirelength.

Energy-Efficient Time Synchronization based on Nonlinear Clock Skew Tracking for Underwater Acoustic Networks

Time synchronization plays an important role in the scheduling and position technologies of sensor nodes in underwater acoustic networks (UANs). The time synchronization (TS) algorithms face challenges such as high requirements of energy efficiency, the estimation accuracy of the time-varying clock skew and the suppression of the impulsive noise. To achieve accurate time synchronization for UANs, an energy-efficient TS method based on nonlinear clock skew tracking (NCST) is proposed. First, based on the sea trial temperature data and the crystal oscillators’ temperature–frequency characteristics, a nonlinear model is established to characterize the dynamic of clock skews. Second, a single-way communication scheme based on a receiver-only (RO) paradigm is used in the NCST-TS to save limited energy. Meanwhile, impulsive noises are considered during the communication process and the Gaussian mixture model (GMM) is employed to fit receiving timestamp errors caused by non-Gaussian noise. To combat the nonlinear and non-Gaussian problem, the particle filter (PF)-based algorithm is used to track the time-varying clock state and an accurate posterior probability density function under the GMM error model is also given in PF. The simulation results show that under the GMM error model, the accumulative Root Mean Square Errors (RMSE) of NCST-TS can be reduced from 10−4 s to 10−5 s compared with existing protocols. It also outperforms the other TS algorithms in the aspect of energy efficiency.

Pair Nodes Clock Synchronization Algorithm Based on Kalman Filter for Underwater Wireless Sensor Networks

Time synchronization is the basis of many applications. Aiming at the limitations of the existing clock synchronization algorithms in underwater wireless sensor networks, we propose a pairwise synchronization algorithm called K-Sync, which is based on the Kalman filter. The algorithm does not need the assistance of the position sensor or the speed sensor, and the high time synchronization accuracy can be realized only by utilizing the time-stamps information in the process of message exchange. The K-Sync uses the general constraints of the motion characteristics of the sensor nodes to establish the recursive equations of the clock skew, clock offset, relative mobility velocity, and relative distance. At the same time, the time-stamps are viewed as the observation variables and the system observation equation is obtained. The K-Sync estimates the normalized clock skew and offset of the node via the Kalman filter to achieve high-precision clock synchronization between the two nodes. The simulation shows that the K-Sync has obvious advantages in the key indicators such as the estimated accuracy of clock skew and clock offset, convergence speed, etc. In addition, the K-Sync is more robust to a variety of underwater motion scenes.